AT45DB021E 2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum SPI Serial Flash Memory PRELIMINARY DATASHEET Features Single 1.65V - 3.
Description The Adesto® AT45DB021E is a 1.65V minimum, serial-interface sequential access Flash memory is ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB021E also supports the RapidS serial interface for applications requiring very high speed operation. Its 2,162,688 bits of memory are organized as 1,024 pages of 256 bytes or 264 bytes each. In addition to the main memory, AT45DB021E also contains one SRAM buffer of 256/264 bytes.
Table 1-1. Pin Configurations Asserted State Type Low Input SCK Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. — Input SI Serial Input: The SI pin is used to shift data into the device.
2. Block Diagram Figure 2-1.
Memory Array To provide optimal flexibility, the AT45DB021E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3-1.
4. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 38 through Table 15-4 on page 39. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the Buffer or main memory address location.
5. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the data buffer. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., "Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3" on page 55 for diagrams detailing the clock cycle sequences for each mode. 5.
5.3 Continuous Array Read (Low Frequency Mode: 03h Opcode) This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence.
5.5 Main Memory Page Read A Main Memory Page Read allows the user to read data directly from any one of the 1,024 pages in the main memory, bypassing the data buffer and leaving the contents of the Buffer unchanged. To start a Main Memory Page Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted then an opcode of D2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes.
6. Program and Erase Commands 6.1 Buffer Write Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into the data buffer. To load data into the Buffer using the standard DataFlash buffer size (264 bytes), an opcode of 84h must be clocked into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0). The nine buffer address bits specify the first byte in the Buffer to be written.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 6.
Example: If only two data bytes were clocked into the device, then only two bytes will be programmed into main memory and the remaining bytes in the memory page will remain in their previous state. The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise the operation will be aborted and no data will be programmed.
Table 6-1. 6.
Table 6-2. 6.
6.10 Read-Modify-Write A completely self-contained read-modify-write operation can be performed to reprogram any number of sequential bytes in a page in the main memory array without affecting the rest of the bytes in the same page. This command allows the device to easily emulate an EEPROM by providing a method to modify a single byte or more in the main memory in a single operation, without the need for pre-erasing the memory or the need for any external RAM buffers.
7. Sector Protection Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin.
7.2 Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as the WP pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted.
7.3 Sector Protection Register The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains eight bytes of data, of which byte locations 0 through 7 contain values that specify whether Sectors 0 through 7 will be protected or unprotected. The Sector Protection Register is user modifiable and must be erased before it can be reprogrammed.
Figure 7-4. Erase Sector Protection Register CS SI 3Dh 2Ah 7Fh CFh Each transition represents eight bits 7.3.2 Program Sector Protection Register Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command. To program the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be clocked into the device followed by eight bytes of data corresponding to Sectors 0 through 7.
7.3.3 Read Sector Protection Register To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin will result in the Sector Protection Register contents being output on the SO pin.
8. Security Features 8.1 Sector Lockdown The device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read-only (ROM). This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Warning: Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.
Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte Value Bit 7:6 Bit 5:4 Bit 3:2 Bit 1:0 Sector 0a (Page 0-7) Sector 0b (Page 8-127) N/A N/A Data Value Sectors 0a and 0b Unlocked 00 00 00 00 00h Sector 0a Locked 11 00 00 00 C0h Sector 0b Locked 00 11 00 00 30h Sectors 0a and 0b Locked 11 11 00 00 F0h Table 8-4. Read Sector Lockdown Register Command Command Read Sector Lockdown Register Byte 1 Byte 2 Byte 3 Byte 4 35h XXh XXh XXh Figure 8-2.
8.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the Security Register are allocated as an One-Time Programmable space. Once these 64 bytes have been programmed, they cannot be erased or reprogrammed.
8.2.2 Reading the Security Register To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output on the SO pin.
9. Additional Commands 9.1 Main Memory Page to Buffer Transfer A page of data can be transferred from the main memory to the Buffer. To transfer a page of data using the standard DataFlash page size (264 bytes), an opcode of 53h must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (PA9 - PA0) which specify the page in main memory to be transferred, and nine dummy bits.
If a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be a page or pages of static data, then the programming algorithm shown in Figure 26-1 on page 59 is recommended; otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the programming algorithm shown in Figure 26-2 on page 60 is recommended.
Table 9-2. Bit 7 Name Type(1) Description RDY/BUSY Ready/Busy Status R 0 Device is busy with an internal operation. 1 Device is ready. 0 Reserved for future use. 0 Erase or program operation was successful. 1 Erase or program error detected. 0 Reserved for future use. 0 Sector Lockdown command is disabled. 1 Sector Lockdown command is enabled.
9.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state. The EPE bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or program a protected region. The EPE bit is updated after every erase and program operation. 9.4.
10. Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode.
10.1 Resume from Deep Power-Down In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognize while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored.
10.2 Ultra-Deep Power-Down The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shut down in this mode to conserve power, the contents of the Buffer cannot be maintained. Therefore, any data stored in the Buffer will be lost once the device enters the Ultra-Deep Power-Down mode.
10.2.1 Exit Ultra-Deep Power-Down To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the minimum necessary tCSLU time, and then deasserting the CS pin again. To facilitate simple software development, a dummy byte opcode can also be entered while the CS pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case.
11. Buffer and Page Size Configuration The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-accessible bytes are provided in each page of the memory array. For the AT45DB021E, there are an extra eight bytes of memory in each page for a total of an extra 8KB (64-Kbits) of user-accessible memory.
12. Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
Table 12-3. EDI Data Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RFU Bit 2 Bit 1 Bit 0 Hex Value Device Revision 1 00h 0 0 0 0 0 0 0 0 Details RFU: Reserved for Future Use Device revision:00000 (Initial Version) Figure 12-1.
13. Software Reset In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The Software Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state.
14. Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. Main Memory Page Read 2. Continuous Array Read (SPI) 3. Read Sector Protection Register 4. Read Sector Lockdown Register 5. Read Security Register Group B commands consist of: 1. Page Erase 2. Block Erase 3. Sector Erase 4. Chip Erase 5. Main Memory Page to the Buffer Transfer 6.
15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2h Continuous Array Read (Low Power Mode) 01h Continuous Array Read (Low Frequency) 03h Continuous Array Read (High Frequency) 0Bh Continuous Array Read (Legacy Command – Not Recommended for New Designs) E8h Buffer Read (Low Frequency) D1h Buffer Read (High Frequency) D4h Table 15-2.
Table 15-3.
Table 15-6.
Table 15-7.
16. Power-On/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the output pin (SO) will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
17. System Considerations The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and will cause improper operation of the device. PCB traces must be kept to a minimum distance or appropriately terminated to ensure proper operation.
18. Electrical Specifications 18.1 Absolute Maximum Ratings* Temperature under Bias-55°C to +125°C Storage Temperature-65°C to +150°C All Input Voltages (except VCC but including NC pins) with Respect to Ground-0.6V to +6.25V All Output Voltages with Respect to Ground-0.6V to VCC + 0.6V 18.2 *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
18.3 DC Characteristics 1.65V to 3.6V Symbol Parameter Condition IUDPD Ultra-Deep PowerDown Current IDPD ISB Min Typ Max Typ Max Units All inputs at 0V or VCC 0.2 1 0.35 1 μA Deep Power-Down Current CS, RESET, WP = VIH All inputs at CMOS levels 4.5 8 5 8 μA Standby Current CS, RESET, WP = VIH All inputs at CMOS levels 22 30 22 30 μA 6 9 7 9 mA f = 10MHz; IOUT = 0mA 6.5 9 7 9 mA f = 20MHz; IOUT = 0mA 6.5 10 7.5 10 mA f = 20MHz; IOUT = 0mA 6.5 10 7.
18.4 AC Characteristics 1.65V to 3.6V Symbol Parameter fSCK SCK Frequency fCAR1 Min Typ 2.3V to 3.6V Max Max Units 70 70 MHz SCK Frequency for Continuous Read 70 70 MHz fCAR2 SCK Frequency for Continuous Read (Low Frequency) 33 33 MHz fCAR3 SCK Frequency for Continuous Read (Low Power Mode – 01h Opcode) 20 20 MHz tWH SCK High Time 6.4 6.4 ns tWL SCK Low Time 6.4 6.4 ns tSCKR(1) SCK Rise Time, Peak-to-peak 0.1 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-peak 0.1 0.
18.5 19. Program and Erase Characteristics Symbol Parameter Min Typ Max Units tEP Page Erase and Programming Time (256/264 bytes) 7 35 ms tP Page Programming Time 1.5 4 ms tBP Byte Programming Time 8 tPE Page Erase Time 6 30 ms tBE Block Erase Time 15 35 ms tSE Sector Erase Time 350 550 ms tCE Chip Erase Time 2.5 4.5 s tOTPP OTP Security Register Program Time 200 500 μs μs Input Test Waveforms and Measurement Levels AC Driving Levels 0.9VCC VCC/2 0.
21. Utilizing the RapidS Function To take advantage of the RapidS function’s ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
Figure 21-2. Command Sequence for Read/Write Operations for Page Size 256 bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (Input) MSB CMD XXXXXX XX 6 Dummy Bits 8-bits 8-bits XXXX XXXX Page Address (A17 - A8) 8-bits XXXX XXXX LSB Byte/Buffer Address (A7 - A0/BFA7 - BFA0) Figure 21-3.
22. AC Waveforms Four different timing waveforms are shown in Figure 22-1 through Figure 22-4. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies only up to 70MHz.
Figure 22-3. Waveform 3 = RapidS Mode 0 tCS CS tWH tCSS tWL tCSH SCK tHO tV SO High-impedance Valid Out tSU SI tDIS High-impedance tH Valid In Figure 22-4.
23. Write Operations The following block diagram and waveforms illustrate the various write sequences available. Figure 23-1. Block Diagram Flash Memory Array Page (256/264 bytes) Buffer To Main Memory Page Program Buffer (256/264 bytes) Buffer Write I/O Interface SI Figure 23-2. Buffer Write Completes Writing into Selected Buffer CS Binary Page Size 16 Dummy Bits + BFA7-BFA0 SI (Input) CMD X X···X, BFA8 BFA7-0 n n+1 Last Byte Figure 23-3.
24. Read Operations The following block diagram and waveforms illustrate the various read sequences available. Figure 24-1. Block Diagram Flash Memory Array Page (256/264 bytes) Main Memory Page To Buffer Buffer (256/264 bytes) Buffer Read Main Memory Page Read I/O Interface SO Figure 24-2.
Figure 24-3. Main Memory Page to Buffer Transfer Data From the selected Flash Page is read into the Buffer Starts Reading Page Data into Buffer CS Binary Page Size A17-A8 + 8 Dummy Bits SI (Input) CMD X...X, PA9-7 PA6-0, X XXXX XXXX SO (Output) Figure 24-4. Buffer Read CS Address for Binary Page Size 16 Dummy Bits + BFA7-BFA0 SI (Input) CMD X X...
25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 Figure 25-1. Continuous Array Read (Legacy Opcode E8h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode SI 1 1 1 0 1 Address Bits 0 0 0 A MSB A A A A A 32 Dummy Bits A A A MSB X X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D D MSB Figure 25-2.
Figure 25-4. Main Memory Page Read (Opcode D2h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode SI 1 1 0 1 0 Address Bits 0 1 0 A MSB A A A A A 32 Dummy Bits A A A MSB X X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D D MSB Figure 25-5.
Figure 25-7. Read Sector Protection Register (Opcode 32h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode SI 0 0 1 1 0 Dummy Bits 0 1 0 X MSB X X X X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D MSB Figure 25-8.
Figure 25-10. Status Register Read (Opcode D7h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK Opcode SI 1 1 0 1 0 1 1 1 MSB Status Register Data High-impedance SO D D D D D D D Status Register Data D MSB D D D D D D D MSB D D D MSB Figure 25-11.
26. Auto Page Rewrite Flowchart Figure 26-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially START Provide Address and Data Buffer Write (84h) Main Memory Page Program through Buffer (82h) Buffer To Main Memory Page Program (83h) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page. 2.
Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array Randomly START Provide Address of Page to Modify Main Memory Page to Buffer Transfer (53h) If planning to modify multiple bytes currently stored within a page of the Flash array Buffer Write (84h) Main Memory Page Program through Buffer (82h) Buffer to Main Memory Page Program (83h) (2) Auto Page Rewrite (58h) Increment Page (2) Address Pointer END Notes: 1.
27. Ordering Information 27.1 Ordering Detail AT 4 5 D B 0 2 1 E - S S H N - B Designator Product Family 45DB = DataFlash Device Density 02 = 2-Mbit Interface 1 = Serial Device Revision Shipping Carrier Option B T Y = Bulk (tubes) = Tape and reel = Trays Operating Voltage N = 1.65V minimum (1.65V to 3.
27.2 Ordering Codes Ordering Code Package AT45DB021E-SSHN-B (1) AT45DB021E-SSHN-T(1) AT45DB021E-SHN-B(1)(2) AT45DB021E-SHN-T(1)(2) AT45DB021E-MHN-Y(1) AT45DB021E-MHN-T(1) AT45DB021E-CCUN-T(1) Notes: 1. 2. Lead Finish Operating Voltage fSCK 1.65V to 3.6V 70MHz Device Grade 8S1 8S2 NiPdAu Industrial (-40C to 85C) 8MA1 9CC1 SnAgCu The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option. Package Type 8S1 8-lead 0.
27.3 Ordering Codes (Binary Page Mode) Ordering Code Package AT45DB021E-SSHN2B-T(1)(3) 8S1 AT45DB021E-SHN2B-T(1)(2)(3) 8S2 AT45DB021E-MHN2B-T (1)(3) 8MA1 Notes: 1. Lead Finish Operating Voltage fSCK NiPdAu 1.65V to 3.6V 70MHz Device Grade Industrial (-40C to 85C) The shipping carrier suffix is not marked on the device. 2. Not recommended for new design. Use the 8S1 package option. 3.
28. Packaging Information 28.1 8S1 – 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
28.2 8S2 – 8-lead EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW A MAX NOM NOTE 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 8° e Notes: 1. 2. 3. 4. MIN 1.70 1.27 BSC 2 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
28.3 8MA1 – 8-pad UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A K E2 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 2 e D2 6 3 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C 5 4 b L BOTTOM VIEW NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.
28.4 9CC1 – 9-ball UBGA Top view d 0.10 (4X) Side View view "A" (rotated 90°CW) E A f 0.10 C d 0.10 C seating plane C Pin#1 ID A A A1 A section A-A See view "A" D B C 1 2 3 B E1 b A1 A A2 Ø0.40±0.05 Ø0.30 ORIGINAL/RAW BALL 9-Øb j n 0.15 m C A B j n 0.05 m C C COMMON DIMENSIONS (Unit of Measure = mm) D1 B SYMBOL MIN NOM MAX A – 0.53 0.60 A1 0.12 – - A e A2 A1 ball corner 1 2 3 D e 0.38 REF 5.90 D1 E b e 6.00 6.10 2.00 BSC 5.
29. Revision History Doc. Rev. Date Comments Corrected pinout diagrms to top view. Added Read-Modify-Write section. For figures Program Sector Protection Register, Read Sector Protection Register Command, and Read Sector Lockdown Register Command, changed the opcode from n +15 to n +7. Add note at end of section, Auto Page Rewrite. Updated figure, Exit Ultr-Deep Power-Down.
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