AT45DB041E 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory ADVANCE DATASHEET Features Single 1.65V - 3.
Description The AT45DB041E is a 1.65V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB041E also supports the RapidS serial interface for applications requiring very high speed operation. Its 4,194,304 bits of memory are organized as 2,048 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB041E also contains two SRAM buffers of 256/264 bytes each.
Table 1-1. Pin Configurations Asserted State Type Low Input SCK Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. — Input SI Serial Input: The SI pin is used to shift data into the device.
2. Block Diagram Figure 2-1.
Memory Array To provide optimal flexibility, the AT45DB041E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3-1.
4. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 40 through Table 15-4 on page 41. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.
5. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode) This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum specified by fCAR1.
of the main memory array to read and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 01h must be clocked into the device followed by three address bytes (A18 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin.
6. Program and Erase Commands 6.1 Buffer Write Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into either one of the SRAM data buffers. To load data into a buffer using the standard DataFlash buffer size (264 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0).
When a low-to-high transition occurs on the CS pin, the device will program the data stored in the appropriate buffer into the specified page in the main memory. The page in main memory that is being programmed must have been previously erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase). The programming of the page is internally self-timed and should take place in a maximum time of tP.
buffer is reached, then the device will wrap around back to the beginning of the buffer. When using the binary page size, the page and buffer address bits correspond to a 19-bit logical address (A18-A0) in the main memory. After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program operation in which the device will program the data stored in Buffer 1 into the main memory array.
6.7 Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer 1 command to be utilized at a later time.
6.9 Sector Erase The Sector Erase command can be used to individually erase any sector in the main memory. The main memory array is comprised of nine sectors, and only one sector can be erased at a time. To perform an erase of Sector 0a or Sector 0b with the standard DataFlash page size (264 bytes), an opcode of 7Ch must be clocked into the device followed by three address bytes comprised of four dummy bits, eight page address bits (PA10 - PA3), and 12 dummy bits.
The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Table 6-3. Chip Erase Command Command Byte 1 Byte 2 Byte 3 Byte 4 Chip Erase C7h 94h 80h 9Ah Figure 6-1. Chip Erase CS C7h 94h 80h 9Ah Each transition represents eight bits 6.
Table 6-4.
6.12 Program/Erase Resume The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue where it left off. To perform a Program/Erase Resume, an opcode of D0h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or erase operation currently suspended will be resumed within a time of tRES.
7. Sector Protection Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin.
Figure 7-2. Disable Sector Protection CS SI 3Dh 2Ah 7Fh 9Ah Each transition represents eight bits 7.2 Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as the WP pin is asserted.
7.3 Sector Protection Register The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains eight bytes of data, of which byte locations zero through seven contain values that specify whether Sectors 0 through 7 will be protected or unprotected. The Sector Protection Register is user modifiable and must be erased before it can be reprogrammed.
Figure 7-4. Erase Sector Protection Register CS SI 3Dh 2Ah 7Fh CFh Each transition represents eight bits 7.3.2 Program Sector Protection Register Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command. To program the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be clocked into the device followed by eight bytes of data corresponding to Sectors 0 through 7.
7.3.3 Read Sector Protection Register To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin will result in the Sector Protection Register contents being output on the SO pin.
8. Security Features 8.1 Sector Lockdown The device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read-only (ROM). This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Warning: Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.
Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte Value Bit 7:6 Bit 5:4 Bit 3:2 Bit 1:0 Sector 0a (Page 0-7) Sector 0b (Page 8-15) N/A N/A Data Value Sectors 0a and 0b Unlocked 00 00 00 00 00h Sector 0a Locked 11 00 00 00 C0h Sector 0b Locked 00 11 00 00 30h Sectors 0a and 0b Locked 11 11 00 00 F0h Table 8-4. Read Sector Lockdown Register Command Command Read Sector Lockdown Register Byte 1 Byte 2 Byte 3 Byte 4 35h XXh XXh XXh Figure 8-2.
8.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the Security Register are allocated as a One-Time Programmable space. Once these 64 bytes have been programmed, they cannot be erased or reprogrammed.
8.2.2 Reading the Security Register To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output on the SO pin.
9. Additional Commands 9.1 Main Memory Page to Buffer Transfer A page of data can be transferred from the main memory to either Buffer 1 or Buffer 2. To transfer a page of data using the standard DataFlash page size (264 bytes), an opcode of 53h for Buffer 1 or 55h for Buffer 2 must be clocked into the device followed by three address bytes comprised of four dummy bits, 11 page address bits (PA10 - PA0) which specify the page in main memory to be transferred, and nine dummy bits.
To initiate an Auto Page Rewrite with the a binary page size (256 bytes), the opcode 58H for Buffer 1 or 59H for Buffer 2, must be clocked into the device followed by three address bytes consisting of three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory that is to be rewritten, and nine dummy bits.
Table 9-2. Status Register Format – Byte 2 Bit Name 7 RDY/BUSY 6 Type(1) Ready/Busy Status R RES Reserved for Future Use R 5 EPE Erase/Program Error R 4 RES Reserved for Future Use R 3 SLE Sector Lockdown Enabled R 2 PS2 Program Suspend Status (Buffer 2) R 1 PS1 Program Suspend Status (Buffer 1) R 0 ES Erase Suspend R Note: 1. R = Readable only 9.4.1 RDY/BUSY Bit Description 0 Device is busy with an internal operation. 1 Device is ready.
9.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state. The EPE bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or program a protected region or a locked down sector or an attempt to erase or program a suspended sector.
10. Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode.
10.1 Resume from Deep Power-Down In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognize while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored.
10.2 Ultra-Deep Power-Down The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shutdown in this mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any data stored in the SRAM buffers will be lost once the device enters the Ultra-Deep Power-Down mode.
10.2.1 Exit Ultra-Deep Power-Down To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the minimum necessary tCSLU time, and then deasserting the CS pin again. To facilitate simple software development, a dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation like the Program Suspend operation; the dummy byte opcode is simply ignored by the device in this case.
11. Buffer and Page Size Configuration The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-accessible bytes are provided in each page of the memory array. For the AT45DB041E, there are an extra eight bytes of memory in each page for a total of an extra 16KB (128-Kbits) of user-accessible memory.
12. Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
Table 12-3. EDI Data Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RFU Bit 2 Bit 1 Bit 0 Hex Value Device Revision 1 00h 0 0 0 0 0 0 0 0 Details RFU: Reserved for Future Use Device revision: 00000 (Initial Version) Figure 12-1.
13. Software Reset In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The Software Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state.
14. Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. Main Memory Page Read 2. Continuous Array Read (SPI) 3. Read Sector Protection Register 4. Read Sector Lockdown Register 5. Read Security Register Group B commands consist of: 1. Page Erase 2. Block Erase 3. Sector Erase 4. Chip Erase 5. Main Memory Page to Buffer 1 (or 2) Transfer 6.
15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2h Continuous Array Read (Low Power Mode) 01h Continuous Array Read (Low Frequency) 03h Continuous Array Read (High Frequency) 0Bh Continuous Array Read (High Frequency) 1Bh Continuous Array Read (Legacy Command – Not Recommended for New Designs) E8h Buffer 1 Read (Low Frequency) D1h Buffer 2 Read (Low Frequency) D3h Buffer 1 Read (High Frequency) D4h Buffer 2 Read (High Frequency) D6h Table 15-2.
Table 15-3.
Table 15-6.
Table 15-7.
16. Power-On/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
17. System Considerations The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. PCB traces must be kept to a minimum distance or appropriately terminated to ensure proper operation.
18. Electrical Specifications 18.1 Absolute Maximum Ratings* Temperature under Bias . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . -65°C to +150°C All Input Voltages (except VCC but including NC pins) with Respect to Ground . . . . . . . . . . -0.6V to 6.25V All Output Voltages with Respect to Ground . . . . . . -0.6V to VCC + 0.6V 18.2 *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
18.3 DC Characteristics Symbol Parameter Condition IUDPD Ultra-Deep Power-Down Current All inputs at 0V or VCC IDPD Deep Power-Down Current ISB Standby Current Active Current, Low Power Read (01h) Operation ICC1 Active Current, Read Operation ICC2(1)(2) Min Typ Max Units 0.4 1 μA CS, RESET, WP = VIH All inputs at CMOS levels 3 10 μA CS, RESET, WP = VIH All inputs at CMOS levels 25 50 μA f = 1MHz; IOUT = 0mA; VCC = 3.6V 6 8 mA f = 10MHz; IOUT = 0mA; VCC = 3.6V 6.
18.4 AC Characteristics Symbol Parameter fSCK SCK Frequency fCAR1 1.65V to 3.6V 2.3V to 3.6V Min Min Max Units 70 85 MHz SCK Frequency for Continuous Read 70 85 MHz fCAR2 SCK Frequency for Continuous Read (Low Frequency) 40 50 MHz fCAR3 SCK Frequency for Continuous Read (Low Power Mode – 01h Opcode) 20 20 MHz tWH SCK High Time 6.4 5.2 ns tWL SCK Low Time 6.4 5.2 ns tSCKR(1) SCK Rise Time, Peak-to-peak 0.1 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-peak 0.1 0.
18.5 Program and Erase Characteristics Symbol Parameter tEP Typ Max Units Page Erase and Programming Time (256/264 bytes) 15 40 ms tP Page Programming Time 3 6 ms tBP Byte Programming Time 8 tPE Page Erase Time 12 35 ms tBE Block Erase Time 45 100 ms tSE Sector Erase Time 1.4 3.
21. Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
Figure 21-2. Command Sequence for Read/Write Operations for Page Size 256 bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) CMD 8-bits 8-bits 8-bits XXXXXXXX XXXXXXXX MSB 5 Dummy Bits Page Address (A18 - A8) XXXXXXXX LSB Byte/Buffer Address (A7 - A0/BFA7 - BFA0) Figure 21-3.
22. AC Waveforms Four different timing waveforms are shown in Figure 22-1 through Figure 22-4. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85MHz.
Figure 22-3. Waveform 3 = RapidS Mode 0 tCS CS tWH tCSS tWL tCSH SCK tHO tV SO High-impedance Valid Out tSU SI tDIS High-impedance tH Valid In Figure 22-4.
23. Write Operations The following block diagram and waveforms illustrate the various write sequences available. Figure 23-1. Block Diagram Flash Memory Array WP Page (256/264 bytes) Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) SCK CS RESET VCC GND I/O Interface SI SO Figure 23-2.
24. Read Operations The following block diagram and waveforms illustrate the various read sequences available. Figure 24-1. Block Diagram Flash Memory Array Page (256/264 bytes) Main Memory Page To Buffer 2 Main Memory Page To Buffer 1 Buffer 1 (256/264 bytes) Buffer 2 (256/264 bytes) Buffer 1 Read Main Memory Page Read Buffer 2 Read I/O Interface SO Figure 24-2.
Figure 24-3. Main Memory Page to Buffer Transfer Data From the selected Flash Page is read into either SRAM Buffer Starts Reading Page Data into Buffer CS Binary Page Size XXXXX, A18-A16 + A15- A8 + 8 Dummy Bits SI (Input) CMD XXXX, PA10-7 PA6-0, XX XXXX XXXX SO (Output) Figure 24-4.
25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 Figure 25-1. Continuous Array Read (Legacy Opcode E8h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode SI 1 1 1 0 Address Bits 1 0 0 A 0 MSB A A A A A 32 Dummy Bits A A A X MSB X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D D MSB Bit 0 of Page n+1 Bit 2048/2112 of Page n Figure 25-2.
Figure 25-4. Main Memory Page Read (Opcode D2h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK Opcode SI 1 1 0 1 0 Address Bits 0 1 A 0 MSB A A A A A 32 Dummy Bits A A A MSB X X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D D MSB Figure 25-5.
Figure 25-7. Read Sector Protection Register (Opcode 32h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK Opcode SI 0 0 1 1 0 Dummy Bits 0 1 0 X MSB X X X X X X X X MSB Data Byte 1 SO High-impedance D D D D D D D D MSB D MSB Figure 25-8.
Figure 25-10. Status Register Read (Opcode D7h) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK Opcode SI 1 1 0 1 0 1 1 1 MSB Status Register Data High-impedance SO D D D D D D D Status Register Data D MSB D D D D D D D D MSB D D MSB Figure 25-11.
26. Auto Page Rewrite Flowchart Figure 26-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially START Provide Address and Data Buffer Write (84h, 87h) Main Memory Page Program through Buffer (82h, 85h) Buffer To Main Memory Page Program (83h, 86h) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page. 2.
Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array Randomly START Provide Address of Page to Modify Main Memory Page to Buffer Transfer (53h, 55h) If planning to modify multiple bytes currently stored within a page of the Flash array Buffer Write (84h, 87h) Main Memory Page Program through Buffer (82h, 85h) Buffer to Main Memory Page Program (83h, 86h) Auto Page Rewrite (58h, 59h) (2) Increment Page (2) Address Pointer END Notes: 1.
27. Ordering Information (Standard DataFlash Page Size) 27.1 Ordering Detail AT 4 5 D B 0 4 1 E - S S H N - B Designator Product Family 45DB = DataFlash Device Density 04 = 4-Mbit Interface 1 = Serial Device Revision Shipping Carrier Option B T Y = Bulk (tubes) = Tape and reel = Trays Operating Voltage N = 1.65V minimum (1.65V to 3.
27.2 Ordering Codes (Standard DataFlash Page Size) Ordering Code Package AT45DB041E-SSHN-B (1) AT45DB041E-SSHN-T(1) AT45DB041E-SHN-B(1)(2) AT45DB041E-SHN-T(1)(2) AT45DB041E-MHN-Y(1) AT45DB041E-MHN-T(1) AT45DB041E-CCUN-T(1) Notes: 1. 2. Lead Finish Operating Voltage fSCK 1.65V to 3.6V 85MHz Device Grade 8S1 8S2 NiPdAu Industrial (-40C to 85C) 8MA1 9CC1 SnAgCu The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option.
27.3 Ordering Codes (Binary Page Size) Ordering Code Package AT45DB041E-SSHN2B-T(1)(3) 8S1 AT45DB041E-SHN2B-T(1)(2)(3) 8S2 AT45DB041E-MHN2B-T (1)(3) 8MA1 Notes: 1. Lead Finish Operating Voltage fSCK NiPdAu 1.65V to 3.6V 85MHz Device Grade Industrial (-40C to 85C) The shipping carrier suffix is not marked on the device. 2. Not recommended for new design. Use the 8S1 package option. 3.
28. Packaging Information 28.1 8S1 – 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
28.2 8S2 – 8-lead EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 A D SIDE VIEW MAX NOM NOTE 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 8° e Notes: 1. 2. 3. 4. MIN 1.70 1.27 BSC 2 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
28.3 8MA1 – 8-pad UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A K E2 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 2 e D2 6 3 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C 5 4 b L BOTTOM VIEW NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.
28.4 9CC1 – 9-ball UBGA Top view d 0.10 (4X) Side View view "A" (rotated 90°CW) E A f 0.10 C d 0.10 C seating plane C Pin#1 ID A A A1 A section A-A See view "A" D B C 1 2 3 B E1 b A1 A A2 Ø0.40±0.05 Ø0.30 ORIGINAL/RAW BALL 9-Øb j n 0.15 m C A B j n 0.05 m C C COMMON DIMENSIONS (Unit of Measure = mm) D1 B SYMBOL MIN NOM MAX A – 0.53 0.60 A1 0.12 – - A e A2 A1 ball corner 1 2 3 D e 0.38 REF 5.90 D1 E b e 6.00 6.10 2.00 BSC 5.
29. Revision History Doc. Rev. Date 8783B 11/2012 8783A 09/2012 Comments Add Legacy Commands table. Update to Adesto. Initial document release.
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