Features • Single 2.5V or 2.7V to 3.
address lines and a parallel interface, the Adesto™ DataFlash® uses a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.
AT45DB081D Table 2-1. Pin Configurations Asserted State Type CS Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
3. Block Diagram FLASH MEMORY ARRAY WP PAGE (256-/264-BYTES) BUFFER 1 (256-/264-BYTES) SCK CS RESET VCC GND BUFFER 2 (256-/264-BYTES) I/O INTERFACE SI SO 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block.
AT45DB081D 5. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 27 through Table 15-7 on page 30. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.
Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
AT45DB081D during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
7. Program and Erase Commands 7.1 Buffer Write Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer (264-bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits and nine buffer address bits (BFA8 - BFA0). The nine buffer address bits specify the first byte in the buffer to be written.
AT45DB081D 7.4 Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (264-bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of three don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be erased and nine don’t care bits.
7.6 Sector Erase The Sector Erase command can be used to individually erase any sector in the main memory. There are 16 sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the DataFlash standard page size (264-bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of three don’t care bits, nine page address bits (PA11 - PA3) and 12 don’t care bits.
AT45DB081D The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Table 7-3. Chip Erase Command Command Byte 1 Byte 2 Byte 3 Byte 4 Chip Erase C7H 94H 80H 9AH Figure 7-1. Chip Erase CS SI Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Each transition represents 8 bits Note: 7.8 Refer to errata regarding Chip Erase on page 52.
8.1 8.1.1 Software Sector Protection Enable Sector Protection Command Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (SI).
AT45DB081D If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used. 9. Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state.
9.1 Sector Protection Register The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains 16-bytes of data, of which byte locations 0 through 15 contain values that specify whether sectors 0 through 15 will be protected or unprotected. The Sector Protection Register is user modifiable and must first be erased before it can be reprogrammed.
AT45DB081D Table 9-4. Erase Sector Protection Register Command Command Erase Sector Protection Register Figure 9-2. Byte 1 Byte 2 Byte 3 Byte 4 3DH 2AH 7FH CFH Erase Sector Protection Register CS SI Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Each transition represents 8 bits 9.1.2 Program Sector Protection Register Command Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command.
Table 9-5. Program Sector Protection Register Command Command Program Sector Protection Register Figure 9-3. Byte 1 Byte 2 Byte 3 Byte 4 3DH 2AH 7FH FCH Program Sector Protection Register CS SI Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Data Byte n Data Byte n+1 Data Byte n + 15 Each transition represents 8 bits 9.1.3 Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted.
AT45DB081D 10. Security Features 10.1 Sector Lockdown The device incorporates a Sector Lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.
10.1.1 Sector Lockdown Register Sector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as shown below: Table 10-2. Sector Lockdown Register Sector Number 0 (0a, 0b) 1 to 15 Locked FFH See Below Unlocked 00H Table 10-3. 10.1.
AT45DB081D 10.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128bytes that is divided into two portions. The first 64-bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64-bytes have been programmed, they cannot be reprogrammed.
10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, the content of the Security Register can be clocked out on the SO pin. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.
AT45DB081D completion of the compare operation, bit six of the status register is updated with the result of the compare. 11.3 Auto Page Rewrite This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit six of the status register. If bit six is a zero, then the data in the main memory page matches the data in the buffer. If bit six is a one, then at least one bit of the data in the main memory page does not match the data in the buffer.
AT45DB081D 12.1 Resume from Deep Power-down The Resume from Deep Power-down command takes the device out of the Deep Power-down mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the CS pin must first be asserted and an opcode of ABH command must be clocked in via input pin (SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to terminate the Deep Power-down mode.
13.1 Programming the Configuration Register To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H.
AT45DB081D 14.1 14.1.1 Manufacturer and Device ID Information Byte 1 – Manufacturer ID JEDEC Assigned Code Hex Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1FH 0 0 0 1 1 1 1 1 14.1.2 Manufacturer ID Byte 2 – Device ID (Part 1) Family Code Density Code Hex Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 25H 0 0 1 0 0 1 0 1 Density Code 14.1.
14.2 Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. 2. 3. 4. 5. Main Memory Page Read Continuous Array Read Read Sector Protection Register Read Sector Lockdown Register Read Security Register Group B commands consist of: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
AT45DB081D 15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2H Continuous Array Read (Legacy Command) E8H Continuous Array Read (Low Frequency) 03H Continuous Array Read (High Frequency) 0BH Buffer 1 Read (Low Frequency) D1H Buffer 2 Read (Low Frequency) D3H Buffer 1 Read D4H Buffer 2 Read D6H Table 15-2.
Table 15-3. Protection and Security Commands Command Opcode Read Sector Lockdown Register Program Security Register 35H 9BH + 00H + 00H + 00H Read Security Register Table 15-4.
AT45DB081D Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes) A0 A1 A2 A3 A4 A5 A6 A7 A8 Address Byte A9 A10 A11 A12 A13 A14 A15 A16 Address Byte A17 A18 A19 Reserved Opcode Reserved Opcode Address Byte Reserved Page Size = 256-bytes Reserved Table 15-6.
Detailed Bit-level Addressing Sequence for the DataFlash Standard Page Size (264-Bytes) Address Byte 1 50h 0 1 0 1 0 0 0 0 x x x P P P P P P P P P x x x x x x x x x x N/A 53h 0 1 0 1 0 0 1 1 x x x P P P P P P P P P P P P x x x x x x x x x N/A 55h 0 1 0 1 0 1 0 1 x x x P P P P P P P P P P P P x x x x x x x x x N/A 58h 0 1 0 1 1 0 0 0 x x x P P P P P P P P P P P P x x x x x x x x x N/A 59h 0 1 0 1 1 0
AT45DB081D 16. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
18. Electrical Specifications Table 18-1. Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C *NOTICE: Storage Temperature..................................... -65C to +150C All Input Voltages (except VCC but including NC pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Table 18-2.
AT45DB081D Table 18-3. DC Characteristics Symbol Parameter Condition IDP Deep Power-down Current ISB Standby Current ICC1 (1) Active Current, Read Operation Min Typ Max Units CS, RESET, WP = VIH, all inputs at CMOS levels 15 25 µA CS, RESET, WP = VIH, all inputs at CMOS levels 25 50 µA f = 20MHz; IOUT = 0mA; VCC = 3.6V 7 10 mA f = 33MHz; IOUT = 0mA; VCC = 3.6V 8 12 mA f = 50MHz; IOUT = 0mA; VCC = 3.6V 10 14 mA f = 66MHz; IOUT = 0mA; VCC = 3.
Table 18-4. AC Characteristics – RapidS/Serial Interface AT45DB081D (2.5V Version) Symbol Parameter fSCK SCK Frequency fCAR1 Max Units 50 66 MHz SCK Frequency for Continuous Array Read 50 66 MHz fCAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 33 MHz tWH SCK High Time 6.8 6.8 ns tWL SCK Low Time 6.8 6.8 ns SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns tSCKF SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.
AT45DB081D 19. Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 1.5V 0.45V AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 20. Output Test Load DEVICE UNDER TEST 30pF 21. AC Waveforms Six different timing waveforms are shown on page 36. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition.
21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU tH VALID IN SI 21.2 tDIS HIGH IMPEDANCE Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO tHO HIGH Z VALID OUT tSU tH VALID IN SI 21.3 tDIS HIGH IMPEDANCE Waveform 3 – RapidS Mode 0 (FMAX = 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU SI 21.
AT45DB081D 21.5 Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
21.6 Reset Timing CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE SO (OUTPUT) HIGH IMPEDANCE SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted 21.7 Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) CMD XXXX XXXX MSB 4 Don’t Care Bits 21.
AT45DB081D 22. Write Operations The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY PAGE (256-/264-BYTES) BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (256-/264-BYTES) BUFFER WRITE I/O INTERFACE SI 22.1 Buffer Write Completes writing into selected buffer CS BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 SI (INPUT) 22.
23. Read Operations The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY PAGE (256-/264-BYTES) MAIN MEMORY PAGE TO BUFFER 2 MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (256-/264-BYTES) BUFFER 2 (256-/264-BYTES) BUFFER 1 READ MAIN MEMORY PAGE READ BUFFER 2 READ I/O INTERFACE SO 23.
AT45DB081D 23.3 Buffer Read CS BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 1 Dummy Byte SI (INPUT) CMD X X BFA7- 0 X..X, BFA9-8 SO (OUTPUT) n n+1 Each transition represents 8 bits 24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3 24.
24.3 Continuous Array Read (Low Frequency: Opcode 03H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A19-A0 0 1 1 MSB A A A A A A A A A MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB 24.
AT45DB081D 24.6 Buffer Read (Low Frequency: Opcode D1H or D3H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 OPCODE SI 1 1 0 1 0 0 0 1 MSB X X X X X X A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB 24.
24.9 Read Security Register (Opcode 77H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 1 1 1 0 DON'T CARE 1 1 1 MSB X X X X X X X X X MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB D MSB 24.
AT45DB081D 25. Auto Page Rewrite Flowchart Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
Figure 25-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) AUTO PAGE REWRITE (58H, 59H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
AT45DB081D 26. Ordering Information 26.1 Ordering Code Detail AT 4 5 DB 0 8 1 D – SSU Designator Product Family Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option Device Density M = 8-pad, 6 x 5 x 1mm MLF (VDFN) SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.209" wide SOIC 8 = 8-megabit Interface 1 = Serial Device Revision 26.
27. Packaging Information 27.1 8M1-A – MLF (VDFN) D D1 0 Pin 1 ID E E1 SIDE VIEW TOP VIEW A3 A2 A1 A 0.08 C Pin #1 Notch (0.20 R) e COMMON DIMENSIONS (Unit of Measure = mm) 0.45 D2 E2 b L K BOTTOM VIEW SYMBOL MIN NOM MAX A – 0.85 1.00 A1 – – 0.05 A2 0.65 TYP A3 0.20 TYP b 0.35 0.40 0.48 D 5.90 6.00 6.10 D1 5.70 5.75 5.80 D2 3.20 3.40 3.60 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 3.80 4.00 4.20 e NOTE 1.27 L 0.50 0.60 0.75 0 – – 12o K 0.
AT45DB081D 27.2 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) A1 D SIDE VIEW SYMBOL MIN A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. MAX NOM NOTE 1.27 BSC L 0.40 – 1.
27.3 8S2 – EIAJ SOIC C 1 E E1 L End View N q Top View e b A A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D Side View Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021mm.
AT45DB081D 28. Revision History Revision Level – Release Date History A – November 2005 Initial Release B – March 2006 Added Preliminary. Added text, in “Programming the Configuration Register”, to indicate that power cycling is required to switch to “power of 2” page size after the opcode enable has been executed. Added “Legacy Commands” table. C – July 2006 Corrected PA3 in opcode 50h for addressing sequence with standard page size. Corrected Chip Erase opcode from 7CH to C7H.
29. Errata 29.
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