Features • • • • • • • • • • • • Single 2.5V - 3.6V or 2.7V - 3.
stream. EEPROM emulation (bit or byte alterability) is easily handled with a selfcontained three step Read-Modify-Write operation.Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode 0 and mode 3.
AT45DB161B Memory Architecture Diagram SECTOR ARCHITECTURE SECTOR 3 = 256 Pages 135,168 bytes (128K + 4K) SECTOR 16 = 256 Pages 135,168 bytes (128K + 4K) PAGE 1 PAGE 6 BLOCK 31 PAGE 7 BLOCK 32 PAGE 8 BLOCK 33 PAGE 9 BLOCK 62 PAGE 14 BLOCK 63 PAGE 15 BLOCK 64 PAGE 16 BLOCK 65 PAGE 17 BLOCK 66 PAGE 18 BLOCK 509 PAGE 4093 BLOCK 510 PAGE 4094 BLOCK 511 Block = 4224 bytes (4K + 128) Device Operation PAGE 0 8 Pages BLOCK 0 BLOCK 30 PAGE ARCHITECTURE BLOCK 1 SECTOR 2 = 256 Pages 1
cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first two bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “Command Sequence for Read/Write Operations” diagram).
AT45DB161B loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, must be followed by the two reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main memory to be written, and ten additional don’t care bits.
AT45DB161B MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. To initiate the operation, an 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the two reserved bits and 22 address bits.
If a sector is programmed or reprogrammed sequentially page-by-page, then the programming algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 on page 27 is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
AT45DB161B WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the WP pin be driven high externally whenever possible.
Table 1. Read Commands Command SCK Mode Opcode Inactive Clock Polarity Low or High 68H SPI Mode 0 or 3 E8H Inactive Clock Polarity Low or High 52H SPI Mode 0 or 3 D2H Inactive Clock Polarity Low or High 54H SPI Mode 0 or 3 D4H Inactive Clock Polarity Low or High 56H SPI Mode 0 or 3 D6H Inactive Clock Polarity Low or High 57H SPI Mode 0 or 3 D7H Continuous Array Read Main Memory Page Read Buffer 1 Read Buffer 2 Read Status Register Read Table 2.
AT45DB161B Table 4.
Absolute Maximum Ratings* *NOTICE: Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AT45DB161B AC Characteristics AT45DB161B (2.
Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 2.0 0.8 0.45V AC MEASUREMENT LEVEL tR, tF < 3 ns (10% to 90%) Output Test Load DEVICE UNDER TEST 30 pF AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams.
AT45DB161B Reset Timing (Inactive Clock Polarity Low Shown) CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. Command Sequence for Read/Write Operations (except Status Register Read) SI MSB r r X X XXXX Reserved for larger densities Notes: CMD 8 bits 8 bits XXXX XXXX Page Address (PA11-PA0) 8 bits XXXX XXXX LSB Byte/Buffer Address (BA9-BA0/BFA9-BFA0) 1.
Write Operations The following block diagram and waveforms illustrate the various write sequences available.
AT45DB161B Read Operations The following block diagram and waveforms illustrate the various read sequences available.
Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 0 1 X X 65 66 67 68 tSU SI tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 4223 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 0 1 0 1 tV SO 18 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 AT45DB161B 2224E–DFLSH–10/02
AT45DB161B Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 42 43 tSU COMMAND OPCODE SI 1 0 1 0 tV HIGH-IMPEDANCE SO DATA OUT D7 MSB D6 D5 Status Register Read (Opcode: 57H) CS SCK 1 2 0 1 3 4 5 6 7 8 1 1 9 10 11 12 16 17 tSU COMMAND OPCODE SI 0 1 0 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D1 D0 LSB D7 MSB 19 2224E–DFLSH–10/
Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 0 X X X tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 4223 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 68 67 tSU COMMAND OPCODE SI 0 1 0 1 0 X X X X X tV SO 20 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 D4 AT45DB161B 2224E–DFLSH–10/02
AT45DB161B Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH-IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: 57H) CS SCK 1 2 3 4 5 6 7 8 9 10 11 12 17 18 tSU COMMAND OPCODE SI 0 1 0 1 0 1 1 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D4 D0 LSB D7 MSB D6 21 2224
Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 62 63 64 1 1 X X X 65 66 67 tSU SI tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 4223 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 1 1 0 1 tV SO HIGH-IMPEDANCE DATA OUT D7 D6 D5 D4 MSB 22 AT45DB161B 2224E–DFLSH–10/02
AT45DB161B Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 42 43 tSU COMMAND OPCODE SI 1 1 1 0 tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D4 D5 MSB Status Register Read (Opcode: D7H) CS SCK 1 2 3 4 5 6 7 8 1 1 9 10 D7 MSB D6 11 12 16 17 tSU COMMAND OPCODE SI 1 1 0 1 0 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D5 D4 D1 D0 LSB D7 MSB 23 2224E–DFLSH–10/02
Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 1 X X X tV HIGH-IMPEDANCE SO DATA OUT D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 4223 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 67 68 tSU COMMAND OPCODE SI 1 1 0 1 0 X X X X X tV SO 24 HIGH-IMPEDANCE DATA OUT D7 MSB D6 D5 D4 AT45DB161B 2224E–DFLSH–10/02
AT45DB161B Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 1 1 0 0 X X X X X tV DATA OUT HIGH-IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: D7H) CS SCK 1 2 3 4 5 6 7 8 9 10 11 12 17 18 tSU COMMAND OPCODE SI 1 1 0 1 0 1 1 1 tV SO HIGH-IMPEDANCE STATUS REGISTER OUTPUT D7 MSB D6 D5 D4 D0 LSB D7 MSB D6 25 2224E–DFLSH–10/02
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 26 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
AT45DB161B Figure 2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
Ordering Information ICC (mA) fSCK (MHz) Active Standby 15 10 20 20 Ordering Code Package Operation Range 0.01 AT45DB161B-CC-2.5 AT45DB161B-RC-2.5 AT45DB161B-TC-2.5 24C1 28R 28T Commercial (0°C to 70°C) 2.5V to 3.6V 10 0.01 AT45DB161B-CC AT45DB161B-RC AT45DB161B-TC 24C1 28R 28T Commercial (0°C to 70°C) 10 0.
AT45DB161B Packaging Information 24C1 – CBGA Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 6.10(0.240) 5.90(0.232) A1 ID 8.10(0.319) 7.90(0.311) SIDE VIEW 0.30 (0.012)MIN TOP VIEW 1.40 (0.055) MAX 1.00 (0.039) REF 4.0 (0.157) 5 4 3 2 1 2.00 (0.079) REF A B 1.00 (0.0394) BSC NON-ACCUMULATIVE 4.0 (0.157) C D E 0.46 (0.018) DIA BALL TYP 1.00 (0.
28R – SOIC B E E1 PIN 1 e D A A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM A 2.39 – 2.79 A1 0.002 – 0.014 D 18.00 – 18.50 E 11.70 – 12.50 E1 8.59 – 8.79 SYMBOL 0º ~ 8º C L Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). MAX B 0.356 – 0.508 C 0.203 – 0.305 L 0.94 – 1.27 e NOTE Note 1 Note 1 1.
AT45DB161B 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.
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