Features • Single 2.5V - 3.6V or 2.7V - 3.
operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the Adesto DataFlash® uses a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size.
AT45DB161D Table 2-1. Pin Configurations Symbol Name and Function Asserte d State Type CS Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
3. Block Diagram FLASH MEMORY ARRAY WP PAGE (512-/528-BYTES) BUFFER 1 (512-/528-BYTES) SCK CS RESET VCC GND RDY/BUSY 4. BUFFER 2 (512-/528-BYTES) I/O INTERFACE SI SO Memory Array To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block.
AT45DB161D 5. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 27 through Table 15-7 on page 30. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.
AT45DB161D 6.4 Main Memory Page Read A main memory page read allows the user to read data directly from any one of the 4,096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the standard DataFlash page size (528-bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes.
7. Program and Erase Commands 7.1 Buffer Write Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer (528-bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written.
AT45DB161D page address bits (A20 - A9) that specify the page in the main memory to be erased and nine don’t care bits. When a low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased state is a logical 1). The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. 7.5 Block Erase A block of eight pages can be erased at one time.
take place in a maximum time of tSE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. Table 7-2. 7.
AT45DB161D 7.8 Main Memory Page Program Through Buffer This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory.
8.1.2 Disable Sector Protection Command To disable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be disabled.
AT45DB161D The table below details the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command. WP Pin and Protection Status Figure 9-1. 1 3 2 WP Table 9-1. 9.
9.1.1 Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin.
AT45DB161D guaranteed. Furthermore, if more than 16-bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if 17-bytes of data are clocked in, then the 17th byte will be stored at byte location 0 of the Sector Protection Register. If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to that byte location cannot be guaranteed.
9.1.4 Various Aspects About the Sector Protection Register The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully evaluate the number of times the Sector Protection Register will be modified during the course of the applications’ life cycle.
AT45DB161D 10.1.1 Sector Lockdown Register Sector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as shown below: Table 10-2. Sector Lockdown Register Sector Number 0 (0a, 0b) 1 to 15 Locked FFH See Below Unlocked 00H Table 10-3.
10.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128-bytes that is divided into two portions. The first 64-bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64-bytes have been programmed, they cannot be reprogrammed.
AT45DB161D 10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the content of the Security Register can be clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.
11.3 Auto Page Rewrite This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory.
AT45DB161D The device density is indicated using bits five, four, three, and two of the status register. For the AT45DB161D, the four bits are 1011 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information. The device density is provided only for backward compatibility. Table 11-1. 12.
Figure 12-2. Resume from Deep Power-Down CS SI Opcode Each transition represents eight bits 13. “Power of 2” Binary Page Size Option “Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size (512-bytes) or standard DataFlash page size (528-bytes).
AT45DB161D 14. Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
14.2 Operation Mode Summary The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. Group A commands consist of: 1. 2. 3. 4. 5. Main Memory Page Read Continuous Array Read Read Sector Protection Register Read Sector Lockdown Register Read Security Register Group B commands consist of: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
AT45DB161D 15. Command Tables Table 15-1. Read Commands Command Opcode Main Memory Page Read D2H Continuous Array Read (Legacy Command) E8H Continuous Array Read (Low Frequency) 03H Continuous Array Read (High Frequency) 0BH Buffer 1 Read (Low Frequency) D1H Buffer 2 Read (Low Frequency) D3H Buffer 1 Read D4H Buffer 2 Read D6H Table 15-2.
Table 15-4. Additional Commands Command Opcode Main Memory Page to Buffer 1 Transfer 53H Main Memory Page to Buffer 2 Transfer 55H Main Memory Page to Buffer 1 Compare 60H Main Memory Page to Buffer 2 Compare 61H Auto Page Rewrite through Buffer 1 58H Auto Page Rewrite through Buffer 2 59H Deep Power-down B9H Resume from Deep Power-down ABH Status Register Read D7H Manufacturer and Device ID Read 9FH Table 15-5.
AT45DB161D Table 15-6.
Table 15-7.
AT45DB161D 16. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
18. Electrical Specifications Table 18-1. Absolute Maximum Ratings* *NOTICE: Temperature under Bias ................. -55°C to +125°C Storage Temperature...................... -65°C to +150°C All Input Voltages (except VCC but including NC pins) with Respect to Ground ....................-0.6V to +6.25V All Output Voltages with Respect to Ground ..............-0.6V to VCC + 0.6V Table 18-2. DC and AC Operating Range Operating Temperature (Case) AT45DB161D (2.
AT45DB161D Table 18-4. AC Characteristics – RapidS/Serial Interface AT45DB161D (2.5V Version) Symbol Parameter fSCK SCK Frequency fCAR1 Max Units 50 66 MHz SCK Frequency for Continuous Array Read 50 66 MHz fCAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 33 MHz tWH SCK High Time 6.8 6.8 ns tWL SCK Low Time 6.8 6.8 ns SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns tSCKF SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.
19. Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V AC MEASUREMENT LEVEL 1.5V 0.45V tR, tF < 2ns (10% to 90%) 20. Output Test Load DEVICE UNDER TEST 30pF 21. AC Waveforms Six different timing waveforms are shown on page 32. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition.
AT45DB161D 21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO tHO HIGH Z VALID OUT tSU tH VALID IN SI 21.3 tDIS HIGH IMPEDANCE Waveform 3 – RapidS Mode 0 (FMAX = 66MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU SI 21.4 tDIS HIGH IMPEDANCE tH VALID IN Waveform 4 – RapidS Mode 3 (FMAX = 66MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO HIGH Z tHO VALID OUT tSU SI 21.
Figure 21-1. RapidS Mode Slave CS 1 8 2 3 4 5 6 1 8 7 2 3 4 5 6 1 7 SCK B E A MOSI C D MSB LSB BYTE-MOSI H G I F MISO MSB LSB BYTE-SO MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master is the host controller and the Slave is the DataFlash The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
AT45DB161D 21.7 Command Sequence for Read/Write Operations for Page Size 512-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB CMD XXX XXXX Don’t Care Bits 21.
22.1 Buffer Write Completes writing into selected buffer CS BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 SI (INPUT) 22.2 X CMD X···X, BFA9-8 BFA7-0 n n+1 Last Byte Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page) Starts self-timed erase/program operation CS BINARY PAGE SIZE A20-A9 + 9 DON'T CARE BITS SI (INPUT) CMD PA11-6 PA5-0, XX Each transition represents eight bits 23.
AT45DB161D 23.1 Main Memory Page Read CS ADDRESS FOR BINARY PAGE SIZE A15-A8 A20-A16 A7-A0 SI (INPUT) CMD PA11-6 , PA5-0, BA9-8 BA7-0 X X 4 Dummy Bytes SO (OUTPUT) 23.2 n n+1 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer) Starts reading page data into buffer CS BINARY PAGE SIZE A20-A9 + 9 DON'T CARE BITS SI (INPUT) CMD PA11-6 PA5-0, XX XXXX XXXX SO (OUTPUT) 23.3 Buffer Read CS BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 SI (INPUT) CMD X X..
24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3 24.1 Continuous Array Read (Legacy Opcode E8H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK OPCODE SI 1 1 1 0 1 ADDRESS BITS 0 0 0 MSB A A A A A A 32 DON'T CARE BITS A A A MSB X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D D MSB BIT 0 OF PAGE n+1 BIT 4095/4223 OF PAGE n 24.
AT45DB161D 24.4 Main Memory Page Read (Opcode: D2H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72 SCK OPCODE SI 1 1 0 1 0 ADDRESS BITS 0 1 0 A MSB A A A A A 32 DON'T CARE BITS A A A MSB X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB 24.
24.7 Read Sector Protection Register (Opcode 32H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 1 1 0 DON'T CARE 0 1 0 X MSB X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB 24.
AT45DB161D 24.10 Status Register Read (Opcode D7H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK OPCODE SI 1 1 0 1 0 1 1 1 MSB STATUS REGISTER DATA HIGH-IMPEDANCE SO D D D D D D D MSB STATUS REGISTER DATA D D D D D D D D MSB D D D MSB 24.
25. Auto Page Rewrite Flowchart Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page 2.
AT45DB161D Figure 25-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) AUTO PAGE REWRITE (58H, 59H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
26. Ordering Information 26.1 Ordering Code Detail AT 4 5 DB 1 6 1 D – SSU Designator Product Family Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option Device Density M S T C 16 = 16-megabit Interface = = = = 8-lead, 6 x 5 x 1mm MLF (VDFN) 8-lead, 0.209" wide SOIC 28-lead, TSOP 24 Ball BGA 1 = Serial Device Revision 26.
AT45DB161D 27. Packaging Information 27.1 8M1-A – MLF (VDFN) D D1 0 Pin 1 ID E E1 SIDE VIEW TOP VIEW A3 A2 A1 A 0.08 C Pin #1 Notch (0.20 R) e COMMON DIMENSIONS (Unit of Measure = mm) 0.45 D2 E2 b L K BOTTOM VIEW SYMBOL MIN NOM MAX A – 0.85 1.00 A1 – – 0.05 A2 0.65 TYP A3 0.20 TYP b 0.35 0.40 0.48 D 5.90 6.00 6.10 D1 5.70 5.75 5.80 D2 3.20 3.40 3.60 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 3.80 4.00 4.20 e NOTE 1.27 L 0.50 0.60 0.
27.2 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position.
AT45DB161D 27.3 28T – TSOP, Type 1 PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15mm per side and on D1 is 0.25mm per side. 3. Lead coplanarity is 0.10mm maximum. MIN MAX NOM A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 NOTE D 13.20 13.
27.4 24C1 - Ball Grid Array Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 6.10(0.240) 5.90(0.232) A1 ID 8.10(0.319) 7.90(0.311) SIDE VIEW 0.30 (0.012)MIN TOP VIEW 1.40 (0.055) MAX 1.00 (0.039) REF 4.0 (0.157) 5 4 3 2 1 2.00 (0.079) REF A B 1.00 (0.0394) BSC NON-ACCUMULATIVE 4.0 (0.157) C D E 0.46 (0.018) DIA BALL TYP 1.00 (0.0394) BSC NON-ACCUMULATIVE BOTTOM VIEW 04/11/01 Package Drawing Contact: contact@adestotech.
AT45DB161D 28. Revision History Doc. Rev. Date 3500O 11/2012 Update to Adesto Technologies. 05/2010 Changed tSE (Typ) 1.6 to 0.7 and (Max) 5 to 1.3 Changed tCE (Typ) TBD to 12 and (Max) TBD to 25 Changed from 10,000 to 20,000 cumulative page erase/program operations and added the please contact Adesto statement in section 11.
29. Errata 29.
Corporate Office California | USA Adesto Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: (+1) 408.400.0578 Email: contact@adestotech.com © 2012 Adesto Technologies. All rights reserved. / Rev.: 3500O–DFLASH–11/2012 Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners.
