Features • Single 2.7V - 3.
sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. To allow for simple in-system reprogrammability, the AT45DB321D does not require high input voltages for programming.
AT45DB321D Table 2-1. Pin Configurations Symbol Name and Function Asserted State Type CS Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
3. Block Diagram FLASH MEMORY ARRAY WP PAGE (512/528 BYTES) BUFFER 1 (512/528 BYTES) SCK CS RESET VCC GND RDY/BUSY BUFFER 2 (512/528 BYTES) I/O INTERFACE SI SO 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block.
AT45DB321D 5. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-7 on page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.
Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
AT45DB321D during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
7. Program and Erase Commands 7.1 Buffer Write Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the DataFlash standard buffer (528 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written.
AT45DB321D 7.4 Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (528 bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to be erased and 10 don’t care bits.
7.6 Sector Erase The Sector Erase command can be used to individually erase any sector in the main memory. There are 64 sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the DataFlash standard page size (528 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit, 10 page address bits (PA12 - PA3) and 13 don’t care bits.
AT45DB321D The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Command Byte 1 Byte 2 Byte 3 Byte 4 Chip Erase C7H 94H 80H 9AH Figure 7-1. Chip Erase CS SI Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Each transition represents 8 bits Note: 7.8 1. Refer to the errata regarding Chip Erase on page 53.
8.1 8.1.1 Software Sector Protection Enable Sector Protection Command Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (SI).
AT45DB321D 9. Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or reprogrammed as long as the WP pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted.
9.1 Sector Protection Register The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains 64 bytes of data, of which byte locations 0 through 63 contain values that specify whether sectors 0 through 63 will be protected or unprotected. The Sector Protection Register is user modifiable and must first be erased before it can be reprogrammed.
AT45DB321D 9.1.1 Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin.
After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Sector Protection Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. If the device is powered-down during the program cycle, then the contents of the Sector Protection Register cannot be guaranteed.
AT45DB321D 9.1.3 Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and 3 dummy bytes must be clocked in via the SI pin. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pins will result in data for the content of the Sector Protection Register being output on the SO pin.
10. Security Features 10.1 Sector Lockdown The device incorporates a Sector Lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.
AT45DB321D 10.1.1 Sector Lockdown Register Sector Lockdown Register is a nonvolatile register that contains 64 bytes of data, as shown below: Sector Number 0 (0a, 0b) 1 to 63 Locked FFH See Below Unlocked 00H Table 10-1. 10.1.
10.2 Security Register The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64 bytes have been programmed, they cannot be reprogrammed.
AT45DB321D 10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the content of the Security Register can be clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.
11.2 Main Memory Page to Buffer Compare A page of data in the main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation for DataFlash standard page size, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed by three address bytes consisting of 1 don’t care bit, 13-page address bits (PA12 - PA0) that specify the page in the main memory that is to be compared to the buffer, and 10 don’t care bits.
AT45DB321D 11.4 Status Register Read The status register can be used to determine the device’s ready/busy status, page size, a Main Memory Page to Buffer Compare operation result, the Sector Protection status or the device density. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the status register, the CS pin must be asserted and the opcode of D7H must be loaded into the device.
12. Deep Power-down After initial power-up, the device will default in standby mode. The Deep Power-down command allows the device to enter into the lowest power consumption mode. To enter the Deep Powerdown mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of B9H command must be clocked in via input pin (SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down operation.
AT45DB321D 13. “Power of 2” Binary Page Size Option “Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size (512 bytes) or DataFlash standard page size (528 bytes). The “power of 2” page size is a onetime programmable configuration register and once the device is configured for “power of 2” page size, it cannot be reconfigured again.
14. Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
AT45DB321D CS SI 9FH Opcode SO 1FH 27H 00H 01H Data Data Manufacturer ID Byte 1 Device ID Byte 2 Device ID Byte 3 Extended Device Information String Length Extended Device Information Byte x Extended Device Information Byte x + 1 Each transition represents 8 bits This information would only be output if the Extended Device Information String Length value was something other than 00H.
Group D commands consist of: 1. Erase Sector Protection Register 2. Program Sector Protection Register 3. Sector Lockdown 4. Program Security Register If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D should not be started. However, during the internally self-timed portion of Group B commands, any command in Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa.
AT45DB321D Table 15-3. Protection and Security Commands Command Opcode Enable Sector Protection 3DH + 2AH + 7FH + A9H Disable Sector Protection 3DH + 2AH + 7FH + 9AH Erase Sector Protection Register 3DH + 2AH + 7FH + CFH Program Sector Protection Register 3DH + 2AH + 7FH + FCH Read Sector Protection Register Sector Lockdown 32H 3DH + 2AH + 7FH + 30H Read Sector Lockdown Register Program Security Register 35H 9BH + 00H + 00H + 00H Read Security Register Table 15-4.
Table 15-6.
AT45DB321D Detailed Bit-level Addressing Sequence for DataFlash Standard Page Size (528 Bytes) BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 Address Byte BA9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 Address Byte PA7 PA8 PA9 PA10 Opcode PA12 Opcode Address Byte Reserved Page Size = 528 bytes PA11 Table 15-7.
16. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. 16.
AT45DB321D 18. Electrical Specifications Table 18-1. Absolute Maximum Ratings* Temperature under Bias ............................... -55° C to +125° C *NOTICE: Storage Temperature .................................... -65° C to +150° C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Table 18-2.
Table 18-4. AC Characteristics – RapidS/Serial Interface AT45DB321D Symbol Parameter fSCK Max Units SCK Frequency 66 MHz fCAR1 SCK Frequency for Continuous Array Read 66 MHz fCAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 MHz tWH SCK High Time 6.8 ns SCK Low Time 6.8 ns tWL (1) Min Typ SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.
AT45DB321D 19. Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 1.5V 0.45V AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 20. Output Test Load DEVICE UNDER TEST 30 pF 21. AC Waveforms Six different timing waveforms are shown on page 36. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition.
21.1 Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66 MHz) tCS CS tWH tCSS tWL tCSH SCK tHO tV SO HIGH IMPEDANCE VALID OUT tSU SI 21.2 tDIS HIGH IMPEDANCE tH VALID IN Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66 MHz) tCS CS tCSS tWL tWH tCSH SCK tV SO tHO HIGH Z VALID OUT tSU tH VALID IN SI 21.
AT45DB321D 21.5 Utilizing the RapidS™ Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
21.6 Reset Timing CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE SO (OUTPUT) HIGH IMPEDANCE SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted. 21.
AT45DB321D 22. Write Operations The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY PAGE (512/528 BYTES) BUFFER 1 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 1 (512/528 BYTES) BUFFER 2 (512/528 BYTES) BUFFER 2 WRITE BUFFER 1 WRITE I/O INTERFACE SI 22.1 Buffer Write Completes writing into selected buffer CS BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 SI (INPUT) 22.
23. Read Operations The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY PAGE (512/528 BYTES) MAIN MEMORY PAGE TO BUFFER 2 MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (512/528 BYTES) BUFFER 2 (512/528 BYTES) BUFFER 1 READ MAIN MEMORY PAGE READ BUFFER 2 READ I/O INTERFACE SO 23.1 Main Memory Page Read CS ADDRESS FOR BINARY PAGE SIZE A15-A8 A21-A16 A7-A0 SI (INPUT) CMD PA12-6 PA5-0, BA9-8 BA7-0 X X 4 Dummy Bytes SO (OUTPUT) 23.
AT45DB321D 23.3 Buffer Read CS BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 SI (INPUT) CMD X X BFA7- 0 X..X, BFA9-8 No Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H) SO (OUTPUT) n n+1 Each transition represents 8 bits 24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3 24.
24.3 Continuous Array Read (Low Frequency: Opcode 03H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A21-A0 0 1 1 MSB A A A A A A A A A MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB 24.
AT45DB321D 24.6 Buffer Read (Low Frequency: Opcode D1H or D3H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 OPCODE SI 1 1 0 1 0 0 0 1 MSB X X X X X X A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D D MSB 24.
24.9 Read Security Register (Opcode 77H) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 1 1 1 0 DON'T CARE 1 1 1 MSB X X X X X X X X X MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB D MSB 24.
AT45DB321D 25. Auto Page Rewrite Flowchart Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
Figure 25-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) AUTO PAGE REWRITE (58H, 59H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
AT45DB321D 26. Ordering Information 26.1 Ordering Code Detail AT 4 5 DB 3 2 1 D – SSU Atmel Designator Product Family Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option Device Density M MW S T 32 = 32-megabit = = = = 8-pad, 6 x 5 x 1 mm MLF (VDFN) 8-pad, 8 x 6 x 1 mm MLF (VDFN) 8-lead, 0.209" wide SOIC 28-lead, TSOP Interface 1 = Serial Device Revision 26.
27. Packaging Information 27.1 8M1-A – MLF (VDFN) D D1 0 Pin 1 ID E E1 SIDE VIEW TOP VIEW A3 A2 A1 A 0.08 C D2 Pin #1 Notch (0.20 R) e COMMON DIMENSIONS (Unit of Measure = mm) 0.45 E2 b SYMBOL MIN NOM MAX A – 0.85 1.00 A1 – – 0.05 A2 0.65 TYP A3 0.20 TYP b L K BOTTOM VIEW 0.35 0.40 0.48 D 5.90 6.00 6.10 D1 5.70 5.75 5.80 D2 3.20 3.40 3.60 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 3.80 4.00 4.20 e NOTE 1.27 L 0.50 0.60 0.75 0 – – 12o K 0.
AT45DB321D 27.2 8MW – MLF (VDFN) D Pin 1 ID SIDE VIEW E A1 TOP VIEW A D1 Pin #1 ID COMMON DIMENSIONS (Unit of Measure = mm) 1 Option A Pin #1 Chamfer (C 0.30) E1 e Option B b L K BOTTOM VIEW Pin #1 Notch (0.20 R) SYMBOL MIN NOM MAX A – – 1.00 A1 – – 0.05 b 0.35 0.40 0.48 D 7.90 8.00 8.10 D1 6.30 6.40 6.50 E 5.90 6.00 6.10 E1 4.70 4.80 4.90 e L NOTE 1.27 0.45 K 0.50 0.55 0.
27.3 8S2 – EIAJ SOIC C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOM MAX NOTE A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e Notes: 1. 2. 3. 4. 5. MIN 1.27 BSC 2, 3 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
AT45DB321D 27.4 28T – TSOP, Type 1 PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.
28. Revision History 52 Revision Level – Release Date History A – November 2005 Initial Release B – January 2006 Added 6 x 5 mm MLF (VDFN) package. Added text, in “Programming the Configuration Register”, to indicate that power cycling is required to switch to “power of 2” page size after the opcode enable has been executed. Corrected typographical error regarding the opcode for chip erase in “Program and Erase Commands” table. C – March 2006 Added Preliminary.
AT45DB321D 29. Errata 29.1 29.1.1 Chip Erase Issue In a certain percentage of units, the Chip Erase feature may not function correctly and may adversely affect device operation. Therefore, it is recommended that the Chip Erase commands (opcodes C7H, 94H, 80H, and 9AH) not be used. 29.1.2 Workaround Use Block Erase (opcode 50H) as an alternative. The Block Erase function is not affected by the Chip Erase issue. 29.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device.
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