Features • Single 2.7V - 3.
However, the use of either interface is purely optional. Its 69,206,016 bits of memory are organized as 8192 pages of 1056 bytes each. In addition to the main memory, the AT45DB642 also contains two SRAM data buffers of 1056 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a selfcontained three step Read-Modify-Write operation.
AT45DB642 Memory Architecture Diagram SECTOR 1 = 248 Pages 261,888 bytes (248K + 7936) SECTOR 0 BLOCK 0 BLOCK 1 SECTOR 1 SECTOR 0 = 8 Pages 8448 bytes (8K + 256) BLOCK ARCHITECTURE BLOCK 2 PAGE ARCHITECTURE 8 Pages PAGE 0 BLOCK 0 SECTOR ARCHITECTURE BLOCK 33 PAGE 9 PAGE 14 PAGE 15 BLOCK 62 PAGE 16 BLOCK 63 PAGE 17 BLOCK 64 PAGE 18 SECTOR 31 = 256 Pages 270,336 bytes (256K + 8K) BLOCK 65 SECTOR 32 = 256 Pages 270,336 bytes (256K + 8K) BLOCK 1022 Device Operation BLOCK 1 SECTOR 2 S
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided.
AT45DB642 As with the Continuous Array Read, the CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. During a Burst Array Read with Synchronous Delay, when the end of a page in main memory is reached (the last bit or the last byte of the page has been clocked out), the system must send an additional 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode) of the next page can be read out.
STATUS REGISTER READ: The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status register will be clocked out on the output pins (SO or I/O7 - I/O0), starting with the next clock cycle.
AT45DB642 BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written and 11 don’t care bits.
Block Erase Addressing PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block 0 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 0 0 0 0 0 0 1 X X X 1 0 0 0 0 0 0 0 0 1 0 X X X 2 0 0 0 0 0 0 0 0 1 1 X X X 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 1 1 1 1 1 1 1 0 0 X X X 1020 1 1 1 1 1 1 1 1 0 1 X X X 1021 1 1 1 1 1 1 1 1 1 0 X X X 1022 1 1 1 1 1
AT45DB642 MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed by three address bytes consisting of 13 page address bits (PA12 - PA0) that specify the page in the main memory that is to be compared to the buffer, and 11 don’t care bits.
This gives the DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. Pin Descriptions SERIAL/PARALLEL INTERFACE CONTROL (SER/PAR): The DataFlash may be configured to utilize either its serial port or parallel port through the use of the serial/parallel control pin (SER/PAR).
AT45DB642 RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences.
Table 1.
AT45DB642 Table 4.
Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AT45DB642 AC Characteristics – Serial/Parallel Interface Symbol Parameter Min Max Units tSPH SER/PAR Hold Time 100 ns tSPS SER/PAR Setup Time 100 ns AC Characteristics – Serial Interface Symbol Parameter fSCK Min Max Units SCK Frequency 20 MHz fCAR SCK Frequency for Continuous Array Read 15 MHz fBARSD SCK Frequency for Burst Array Read with Synchronous Delay 20 MHz tWH SCK High Time 22 ns tWL SCK Low Time 22 ns tCS Minimum CS High Time 250 ns tCSS CS Setup Time 25
AC Characteristics – Parallel Interface Symbol Parameter fSCK1 Min Max Units CLK Frequency 5 MHz fCAR1 CLK Frequency for Continuous Array Read 3 MHz fBARSD1 CLK Frequency for Burst Array Read with Synchronous Delay 5 MHz tWH CLK High Time 80 ns tWL CLK Low Time 80 ns tCS Minimum CS High Time 250 ns tCSS CS Setup Time 250 ns tCSH CS Hold Time 250 ns tCSB CS High to RDY/BUSY Low tSU Data In Setup Time 75 ns tH Data In Hold Time 25 ns tHO Output Hold Time 0 ns
AT45DB642 AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK/CLK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK/CLK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the input signals (SI or I/O7-I/O0) are referenced to the low-to-high transition on the SCK/CLK signal.
Reset Timing (Inactive Clock Polarity Low Shown) CS tREC tCSS SCK/CLK tRST RESET HIGH IMPEDANCE HIGH IMPEDANCE SO or I/O7 - I/O0 (OUTPUT) SI or I/O7 - I/O0 (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted.
AT45DB642 Write Operations The following block diagram and waveforms illustrate the various write sequences available.
Read Operations The following block diagram and waveforms illustrate the various read sequences available.
AT45DB642 Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 0 1 X X 65 66 67 68 tSU SI tV DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 8447 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: 69H) CS SCK 1 2 63 64 65 66 67 1 0 1 X 32 33 X tV SO 31 32 CLOCKS tSU SI 2 HIGH IMPEDANCE DATA OUT D7 D6 LSB D1 D0 BIT 8447 OF PAGE n MSB Don't Care D
Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 1 0 1 0 tV DATA OUT HIGH IMPEDANCE SO D7 MSB D6 42 43 D5 Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 tSU COMMAND OPCODE SI 1 0 1 0 tV HIGH IMPEDANCE SO DATA OUT D7 MSB D6 D5 Status Register Read (Opcode: 57H) CS SCK 1 2 0 1
AT45DB642 Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 0 X X X tV DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 8447 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: 69H) CS SCK 1 63 2 64 65 1 66 0 1 X X 33 X tV SO 32 32 CLOCKS tSU SI 31 2 HIGH IMPEDANCE DATA OUT D7 D6 LSB D1 D0 BIT 8447 OF PAGE n MSB Don't Care D7
Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 68 67 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH IMPEDANCE SO D7 MSB D6 D5 D4 Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: 57H) CS SCK
AT45DB642 Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 62 63 64 1 1 X X X 65 66 67 tSU SI tV DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 8447 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: E9H) CS SCK 1 2 62 63 64 65 1 66 0 1 X X 32 33 X tV SO 31 32 CLOCKS tSU SI 2 HIGH IMPEDANCE DATA OUT D7 D6 LSB D1 D0 BIT 8447 OF PAGE n MSB Don't Care D7 D6 BIT
Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 60 61 62 63 64 0 X X X X X 65 66 67 tSU COMMAND OPCODE SI 1 1 1 0 tV DATA OUT HIGH IMPEDANCE SO D7 D6 D5 42 43 D4 MSB Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 3 4 5 36 37 38 39 40 0 X X X X X 41 tSU COMMAND OPCODE SI 1 1 1 0 tV HIGH IMPEDANCE SO DATA OUT D7 D6 D4 D5 MSB Status Register Read (Opcode: D7H) CS SCK 1 2 1 1 3 4
AT45DB642 Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 0 X X X tV DATA OUT HIGH IMPEDANCE SO D7 D6 D5 D2 D1 LSB MSB D0 D7 BIT 8447 OF PAGE n D6 D5 BIT 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: E9H) CS SCK 1 63 2 64 65 1 66 0 1 X X 33 X tV SO 32 32 CLOCKS tSU SI 31 2 HIGH IMPEDANCE DATA OUT D7 D6 LSB D1 D0 BIT 8447 OF PAGE n MSB Don't Care D7 D6 BIT 0 OF PAG
Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 3 4 5 61 62 63 64 65 66 67 68 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH IMPEDANCE SO D7 MSB D6 D5 D4 Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 3 4 5 37 38 39 40 41 42 43 44 tSU COMMAND OPCODE SI 1 0 1 0 0 X X X X X tV DATA OUT HIGH IMPEDANCE SO D7 MSB D6 D5 D4 Status Register Read (Opcode: D7H) CS SCK 1 2 3 4 5 6
AT45DB642 Detailed Parallel Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS CLK 1 2 62 63 64 CMD ADDR X X X 65 66 67 tSU I/O7-I/O0 (INPUT) tV I/O7-I/O0 (OUTPUT) DATA OUT HIGH IMPEDANCE DATA DATA DATA DATA DATA DATA DATA DATA DATA BYTE 1055 OF PAGE n BYTE 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: E9H) CS CLK 1 2 62 63 64 65 1 66 CMD ADDR X X 32 33 X tV I/O7-I/O0 (OUTPUT) 31 32 CLOCKS tSU I/O7-I/O0 (INPUT) 2 HIGH IMPEDANCE DATA
Detailed Parallel Timing – SPI Mode 0 (Continued) Main Memory Page Read (Opcode: D2H) CS CLK 1 2 3 4 5 60 61 62 63 64 X X X X X X 65 66 67 tSU I/O7-I/O0 (INPUT) COMMAND OPCODE CMD ADDR ADDR ADDR tV HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) DATA OUT DATA DATA DATA DATA Buffer Read (Opcode: D4H or D6H) CS CLK 1 2 3 4 6 5 7 tSU COMMAND OPCODE I/O7-I/O0 (INPUT) CMD ADDR ADDR X ADDR tV DATA OUT HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) DATA DATA DATA MSB Status Register Read (Op
AT45DB642 Detailed Parallel Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS CLK 1 2 63 64 65 66 67 tSU I/O7-I/O0 (INPUT) CMD ADDR X X X tV DATA OUT HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) DATA DATA DATA DATA DATA DATA DATA DATA DATA BYTE 1055 OF PAGE n BYTE 0 OF PAGE n+1 Burst Array Read with Synchronous Delay (Opcode: E9H) CS CLK 1 63 2 64 65 1 66 I/O7-I/O0 (OUTPUT) 32 33 32 CLOCKS tSU I/O7-I/O0 (INPUT) 31 2 CMD ADDR X X X tV HIGH IMPEDANCE DATA OUT DATA
Detailed Parallel Read Timing – SPI Mode 3 (Continued) Main Memory Page Read (Opcode: D2H) CS CLK 1 2 3 4 5 61 62 63 64 65 66 67 68 tSU I/07-I/O0 (INPUT) COMMAND OPCODE CMD ADDR ADDR ADDR X X X X X X tV DATA OUT HIGH IMPEDANCE I/07-I/O0 (OUTPUT) DATA DATA DATA DATA Buffer Read (Opcode: D4H or D6H) CS CLK 1 2 3 4 5 6 7 8 9 tSU I/O7-I/O0 (INPUT) CMD ADDR ADDR ADDR X tV HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) DATA OUT DATA DATA DATA DATA Status Register Read (Opcode: D7
AT45DB642 Figure 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2.
Figure 2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) AUTO PAGE REWRITE (58H, 59H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1.
AT45DB642 Ordering Information fSCK (MHz) 20 ICC (mA) Active (1) Ordering Code Package 0.01 AT45DB642-TC 40T Commercial (0°C to 70°C) 10(1) 0.01 AT45DB642-TI 40T Industrial (-40°C to 85°C) 10 20(1) Note: Standby (1) Operation Range 1.
Packaging Information 40T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. NOTE A2 0.95 1.00 1.05 D 19.
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