Manual

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Features

• Single-voltage Operation

–5V Read

– 5V Programming

• Fast Read Access Time – 90 ns

• Internal Erase/Program Control

• Sector Architecture

– One 8K Word (16K Bytes) Boot Block with Programming Lockout

– Two 4K Word (8K Bytes) Parameter Blocks

– One 496K Word (992K Bytes) Main Memory Array Block

• Fast Sector Erase Time – 10 seconds

• Byte-by-byte or Word-by-word Programming – 10 µs Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49F008A(T) and AT49F8192A(T) are 5-volt, 8-megabit Flash memories orga-

nized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured

with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times

to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby

current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of

the feature are available: the AT49F008A/8192A locates the boot block at lowest

order addresses (“bottom boot”); the AT49F008AT/8192AT locates it at highest order

addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49F008A(T)/8192A(T) does

not require high-input voltages for programming. Reading data out of the device is

similar to reading from an EPROM; it has standard CE

, OE and WE inputs to avoid

bus contention. Reprogramming the AT49F008A(T)/8192A(T) is performed by first

erasing a block of data and then programming on a byte-by-byte or word-by-word

basis.

8-megabit

(1M x 8/

512K x 16)

Flash Memory

AT49F008A

AT49F008AT

AT49F8192A

AT49F8192AT

Rev. 1199F–04/01

Pin Configurations

Pin Name Function

A0 - A18 Addresses

Chip Enable

Output Enable

WE Write Enable

RESET

Reset

RDY/BUSY

Ready/Busy Output

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE

Selects Byte or Word Mode

NC No Connect

(continued)

Summary of content (15 pages)

PAGE 1
Features • Single-voltage Operation • • • • • • • • • – 5V Read – 5V Programming Fast Read Access Time – 90 ns Internal Erase/Program Control Sector Architecture – One 8K Word (16K Bytes) Boot Block with Programming Lockout – Two 4K Word (8K Bytes) Parameter Blocks – One 496K Word (992K Bytes) Main Memory Array Block Fast Sector Erase Time – 10 seconds Byte-by-byte or Word-by-word Programming – 10 µs Typical Hardware Data Protection Data Polling for End of Program Detection Low Power Dissipation – 50 mA A
PAGE 2
AT49F8192A(T) TSOP Top View Type 1 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AT49F8192A(T) SOIC (SOP) Top View NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 A16 BYTE GND I/O15 / A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0 1 2 3 4 5
PAGE 3
AT49F008A(T)/8192A(T) AT49F008A(T) Block Diagram AT49F008A VCC AT49F008AT DATA INPUTS/OUTPUTS I/O0 - I/O7 DATA INPUTS/OUTPUTS I/O0 - I/O7 INPUT/OUTPUT BUFFERS INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES PROGRAM DATA LATCHES GND OE WE CE RESET CONTROL LOGIC Y DECODER ADDRESS INPUTS X DECODER Y-GATING MAIN MEMORY (992K BYTES) PARAMETER BLOCK 2 8K BYTES PARAMETER BLOCK 1 8K BYTES BOOT BLOCK 16K BYTES Y-GATING FFFFF 08000 07FFF 06000 05FFF 04000 03FFF 00000 BOOT BLOCK 16K BYTES PARAMETER BLOCK 1
PAGE 4
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.
PAGE 5
AT49F008A(T)/8192A(T) hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes” (for hardware operation) or “Software Product Identification Entry/Exit” on page 12. The manufacturer and device codes are the same for both modes. DATA POLLING: The AT49F008A(T)/8192A(T) features Data Polling to indicate the end of a program cycle.
PAGE 6
Command Definition in Hex(1) Command Sequence 1st Bus Cycle Bus Cycles Addr Data Read 1 Addr DOUT Chip Erase 6 5555 AA 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Data Addr Data Addr Data Addr Data Addr Data 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 2AAA 55 (4) SA 30 2AAA 55 5555 40 6 5555 AA 2AAA 55 5555 80 5555 AA Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA Product ID Entry
PAGE 7
AT49F008A(T)/8192A(T) DC and AC Operating Range AT49F008A/8192A(T)-90 0°C - 70°C Com. Operating Temperature (Case) -40°C - 85°C Ind.
PAGE 8
AC Read Characteristics AT49F008A/8192A(T)-90 Symbol Parameter tACC Min Max Units Address to Output Delay 90 ns tCE(1) CE to Output Delay 90 ns tOE(2) OE to Output Delay 0 40 ns tDF(3)(4) CE or OE to Output Float 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tRO RESET to Output Delay ns 800 ns AC Read Waveforms(1)(2)(3)(4) ADDRESS ADDRESS VALID CE t CE t OE OE t DF t t OH ACC t RO RESET OUTPUT Notes: HIGH Z OUTPUT VALID 1.
PAGE 9
AT49F008A(T)/8192A(T) AC Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 50 ns tDS Data Setup Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 40 ns AC Byte/Word Load Waveforms WE Controlled CE Controlled 9 1199F–04/01
PAGE 10
Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Byte/Word Programming Time 10 50 µs tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 50 ns tWPH Write Pulse Width High 40 ns tEC Erase Cycle Time 5 seconds Program Cycle Waveforms PROGRAM CYCLE OE CE t WP t BP t WPH WE t AS A0-A18 t DH t AH 5555 5555 2AAA 5555 ADDRESS t DS 55 AA DATA A0 AA INPUT DATA Secto
PAGE 11
AT49F008A(T)/8192A(T) Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max OE to Output Delay tWR Write Recovery Time Units 10 ns 10 ns (2) tOE Notes: Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in “AC Read Characteristics” on page 8.
PAGE 12
Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555(7) Boot Block Lockout Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555(3) LOAD DATA 55 TO ADDRESS 2AAA(7) LOAD DATA 55 TO ADDRESS 2AAA(3) LOAD DATA 90 TO ADDRESS 5555(7) LOAD DATA 80 TO ADDRESS 5555(3) ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 5555(3) Software Product Identification Exit(1)(6) LOAD DATA AA TO ADDRESS 5555(7) LOAD DATA 55 TO ADDRESS 2AAA(7) OR LOAD DATA 55 TO ADDRESS 2AAA(3) LOAD DATA F
PAGE 13
AT49F008A(T)/8192A(T) AT49F008A Ordering Information tACC (ns) 90 ICC (mA) Standby Active 50 0.3 Ordering Code Package Operation Range AT49F008A-90TI 40T Industrial (-40° to 85°C) Package Operation Range AT49F8192A(T) Ordering Information ICC (mA) tACC (ns) Active Standby 90 50 0.3 AT49F8192A-90TC 48T Commercial (0° to 70°C) 90 50 0.3 AT49F8192AT-90RC AT49F8192AT-90TC 44R 48T Commercial (0° to 70°C) Ordering Code Package Type 44R 44-lead, 0.
PAGE 14
Packaging Information 44R, 44-lead, 0.
PAGE 15
Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 1150 E. Cheyenne Mtn. Blvd.