Features ARM7TDMI™ ARM® Thumb™ Processor Core One 16-bit Fixed-point OakDSPCore® Dual Ethernet 10/100 Mbps MAC Interface with Voice Priority Multi-layer AMBA™ Architecture 256 x 32-bit Boot ROM 88K bytes of Integrated Fast RAM Flexible External Bus Interface with Programmable Chip Selects Codec Interface Multi-level Priority, Individually-maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Additional Watchdog Timer Two USARTs with FIFO and Modem Control Lines Industry-standard Serial Periphe
AT75C220 Pin Configuration 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VDD3V3 B0256 GND DBW32 VDD3V3 PB9 PB8/NCE2 PB7/NCE1 PB6/NWDOVF PB5/NRIA PB4 PB3/NCTSA PB2/TIOB1 PB1/TIOA1 PB0/TCLK1 GND TXDB RXDB NDCDA NDSRA NDTRA NCTSA NRTSA TXDA RXDA GND PA0/OAKAIN0 PA1/OAKAIN1 PA2/OAKAOUT0 PA3/OAKAOUT1 PA4 PA5 NC VDD3V3 PA6 PA7 PA8/TCLK0 PA9/TIOA0 PA10/
AT75C220 Pin Description Table 1.
Table 1.
AT75C220 Table 1.
Figure 2.
AT75C220 Figure 3. DSP Subsystem Block Diagram Oak Program Bus Oak Data Bus 2K x 16 X-RAM Codec Interface 2K x 16 Y-RAM 24K x 16 Program RAM 16K x 16 Generalpurpose RAM OakDSPCore 256 x 16 Dual-port Mailbox On-chip Emulation Module Bus Interface Unit DSP Subsystem ASB Figure 4.
Architectural Overview The AT75C220 integrates an embedded ARM7TDMI processor. External SDRAM and SRAM/Flash interfaces are provided so that processor code and data may be stored off-chip. peripheral has 16K bytes of address space allocated in the upper part of the address space. The peripheral register set is composed of control, mode, data, status and interrupt registers. The AT75C220 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).
AT75C220 Memory Map The memory map is divided into regions of 256 megabytes. The top memory region (0xF000_0000) is reserved and subdivided for internal memory blocks or peripherals within the AT75C220. The device can define up to six other active external memory regions by means of the static memory controller and SDRAM memory controller. See Table 2. The memory map is divided between the two ASB buses. All regions except the 16 megabytes between 0xFB00_0000 and 0xFBFF_FFFF are located on the ARM ASB bus.
Peripheral Memory Map The register maps for each peripheral are described in the corresponding section of this datasheet. The peripheral memory map has 16K bytes reserved for each peripheral. Table 3.
AT75C220 Clocking The AT75C220 mode register controls clock generation. Oak System Clock Oscillator and PLL The Oak subsystem runs at 60MHz. The AT75C220 uses an external 16 MHz crystal (XCLK) and an on-chip PLL to generate the internal clocks. The PLL generates a 240 MHz clock that is divided down to produce the ARM clock and Oak clock. Other Clocks The codec interfaces run from 800 kHz that is seperate from the Oak clock. The USARTs and timers operate from divided ARM clocks.
AT75C220 Mode Controller The ARM configures the mode of the AT75C220 by means of the SIAP-E mode controller. The SIAP-E mode controller is a memory-mapped peripheral that sits on the APB bus. Register Map Base Address: 0xFF000000 Table 5.
AT75C220 • SA: Slow ARM Mode On reset this field is low. In normal operating mode, if bit SA is set. The ARM clock is 34Mhz (i.e. the PLL value is divided by 7). IF SA is not set the ARM clock is 40MHz (i..e the PLL divisor is 6). SA can be switched during low power mode but should not be changed when LP is low. • LPCS: Low Power Clock Select This field is used to select a slower clock frequency for the ARM system clock as per the table below.
• OUTDIV Output frequency range of PLL. OUTDIV • PLL Output Frequency Range 0 0 40 MHz to 250 MHz 0 1 20 MHz to 40 MHz 1 0 10 MHz to 20 MHz 1 1 5 MHz to 10 MHz JCIDBG This field controls the mode of the JCI. The Oak subsystem has its own JTAG port. This port is used to communicate serially with the Oak OCEM module.
AT75C220 SIAP-E Reset Status Register Register Name: SIAP_RST Access: Read/write Reset Value: 0x00000001 • 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 RST 1 RST 0 RST RST[2:0]: Reset These bits indicate the cause of the last reset.
External Bus Interface The external bus interface (EBI) generates the signals which control access to external memories or peripheral devices. SMC: Static Memory Controller The static memory controller (SMC) is used by the AT75C220 to access external static memory devices. Static memory devices include external Flash, SRAM or peripherals. The SMC provides a glueless memory interface to external memory using the common address and data bus and some dedicated control signals.
AT75C220 For a 32-bit bus: • The signal NWE0 is used as the write enable signal for byte 0. • The signal NWE1 is used as the write enable signal for byte 1. • The signal NWE2 is used as the write enable signal for byte 2. • The signal NWE3 is used as the write enable signal for byte 3. • The signal NSOE enables memory reads to all memory blocks. For a 16-bit bus: • The signal NWE0 is used as the write enable signal for byte 0. • The signal NWE1 is used as the write enable signal for byte 1.
valid longer than in standard read protocol due to the additional wait cycle that follows a write access. Wait States The SMC can automatically insert wait states.
AT75C220 SMC Register Map The SMC is programmed using the registers listed in the Table 8. The memory control register (SMC_MCR) is used to program the number of active chip selects and data read protocol. Four chip select registers (SMC_CSR0 to SMC_CSR3) are used to program the parameters for the individual external memories. Each SMC_CSR must be programmed with a different base address, even for unused chip selects. The AT75C220 resets such that SMC_CSR0 is configured as having a 16-bit data bus.
• NWS: Number of Wait States This field is valid only if WSE is set. Table 9.
AT75C220 • CSEN: Chip Select Enable Active high. • LCD: LCD Mode Enable Active high. SMC_CSR3 only. • BA: Base Address This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of the base address are ignored by the SMC decoder.
Switching Waveforms Figure 6 shows a write to memory 0 followed by a write and a read to memory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 0. SMC_MCR is programmed for early reads from all memories. As BAT = 1, they are configured as byte select signals and have the same timing as NCE. As the access has no internal wait states, the write strobe pulse is one- half clock cycle long.
AT75C220 Figure 7 shows a write and a read to memory 0 followed by a read and a write to memory 1. SMC_CSR0 is programmed for zero wait states with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 1. SMC_MCR is programmed for normal reads from all memories The write to memory 0 is a byte access and, therefore, only one NWE strobe is active. As BAT = 0, they are configured as write strobes and have the same timing as NWR.
SDMC: SDRAM Controller The AT75C220 integrates an SDRAM controller (SDMC). The ARM accesses external SDRAM by means of the SDRAM memory controller. Main features of the SDMC are: • External memory mapping • Up to 4 chip select lines The SDMC shares the same address and data pins as the static memory controller but has separate control signals. • 32- or 16-bit data bus The SDMC interface is a memory-mapped APB slave.
AT75C220 Figure 8. Read with Burst Length of 4 and CAS Latency of 2 BCLK BA BTRAN A0 A1 A2 A3 NSEQ SEQ SEQ SEQ NSEQ NOP NOP D2 D3 BWAIT SDRAM CMD NOP addr PRE NOP BANK ACT NOP ROW READ READ READ READ COL0 COL1 COL2 COL3 D0 D1 sdmc_data BD D0 D1 D2 NOP D3 Figure 9.
Figure 10. Read Showing a Single Access for a Non-sequential Read to a New Row BCLK BA A0 A1 BTRAN NSEQ NSEQ hburst_h INCR INCR BWAIT SDRAM CMD NOP Addr PRE NOP ACT BANK ROW NOP READ NOP COL0 COL1 NOP NOP D0 sdmc_data BD D0 SDRAM Refresh Writes can burst continuously until any of the following conditions are achieved: Table 11 shows the counter values needed for a refresh rate of 15.625 µs in the SDMC.
AT75C220 SDMC Register Map Base Address: 0xFF008000 Table 12.
SDRAM_TIMER Register Register Name: SDRAM_TIMER Access Type: Read/write Reset Value: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 CNT 3 2 CNT • CNT This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
AT75C220 • • NR Sets the number of row bits. Default is 11 row bits. NR Row Bits 00 11 01 12 10 13 11 Reserved NB Sets the number of banks. Default is two banks. NB Number of Banks 0 2 1 4 • CAS Sets the CAS latency. The SDMC has been modified so that it only supports a CAS latency of two. Writing to this register will have no effect. • TWR Sets the value of TWR expressed in number of cycles. Default is two cycles. • TRC Sets the value of TRC expressed in number of cycles.
SDRAM_CS0_ADDR Register Register Name: SDRAM_CS0_ADDR Access Type: Read/write Reset Value: 0x40 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CS0_ADDR 7 6 5 4 3 2 1 0 CS0_ADDR • CS0_ADDR This bit is used to set the eight most significant bits of the address of CS0.
AT75C220 Arbitration Using Multi-layer AMBA The AT75C220 has two separate ASB (multi-layer AMBA) buses that can be decoupled during most normal operations. The ability to couple the two ASB buses is provided to allow the ARM to receive and transmit Ethernet frames via the two Ethernet MACs. The ARM bus is the main processor bus to which most peripherals are connected. The MAC bus is used exclusively for Ethernet traffic.
Figure 12.
AT75C220 Ethernet MAC The AT75C220 integrates two identical Ethernet MACs, known as MAC A and MAC B. The Ethernet MAC is described more fully in the IEEE standard 802.3. It is a programmable device on the APB bus by means of 56 configuration and status registers. The Ethernet MAC is an ASB master. The main features of the Ethernet MAC are: • Compatibility with IEEE standard 802.
another buffer can be safely queued. An interrupt is generated whenever this bit is set. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO wordby-word. If necessary, padding is added to make the frame length 60 bytes. The CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. The CRC is not appended if the NCRC bit is set in the transmit control register.
AT75C220 Table 14. Received Buffer Descriptor List Bit Function Word 0 31:2 Address of beginning of buffer 1 Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue pointer register to give the pointer to entries in this table will be cleared after the buffer is used. 0 Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA owns the buffer.
hash matched frames. So all multicast frames can be received by setting all bits in the hash register. whether the frame is multicast or unicast and the appropriate match signals will be sent to the DMA block The CRC algorithm reduces the destination address to a 6bit index into a 64-bit hash register.
AT75C220 Table 15.
• MPE Management port enable. Set to one to enable the management port. When zero forces MDIO to high impedance state. • CSR Clear statistics registers. This bit is write-only. Writing a one clears the statistics registers. • ISR Increment statistics registers. This bit is write-only. Writing a one increments all the statistics registers by one for test purposes. • WES Write enable for statistics registers. Setting this bit to one makes the statistics registers writable for functional test purposes.
AT75C220 • BIG Receive 1522 bytes. When set, the MAC will receive up to 1522 bytes. Normally the MAC will receive frames up to 1518 bytes in length. • EAE External address match enable. Optional. • CLK The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). For conformance with IEEE 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
MAC Transmit Address Register Register Name: ETH_TAR Access Type: Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS • ADDRESS Transmit address register. Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note if the two least significant bits are not zero, transmit will start at the byte indicated.
AT75C220 MAC Transmit Status Register Register Name: ETH_TSR Access Type: Read/write Reset Value: 0x18 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – UND COMP BNQ IDLE RLE COL OVR • OVR Ethernet transmit buffer overrun. Software wrote to the address register or length register when bit 4 was not set. Cleared by writing a one to this bit.
MAC Receive Buffer Queue Pointer Register Name: ETH_RBQP Access Type: Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS • ADDRESS Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.
AT75C220 MAC Interrupt Status Register Register Name: ETH_ISR Access Type: Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – HRESP ROVR LINK TIDLE 7 6 5 4 3 2 1 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE Management done. The PHY maintenance register has completed its operation. Cleared on read. • RCOM Receive complete.
MAC Interrupt Enable Register Register Name: ETH_IER Access Type: Write-only Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – HRESP ROVR LINK TIDLE 7 6 5 4 3 2 1 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE Enable management done interrupt. • RCOM Enable receive complete interrupt. • RBNA Enable receive buffer not available interrupt.
AT75C220 MAC Interrupt Disable Register Register Name: ETH_IDR Access Type: Write-only Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – HRESP ROVR LINK TIDLE 7 6 5 4 3 2 1 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE Disable management done interrupt. • RCOM Disable receive complete interrupt. • RBNA Disable receive buffer not available interrupt.
MAC Interrupt Mask Register Register Name: ETH_IMR Access Type: Read-only Reset Value: 0xFFFF 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – HRESP ROVR LINK TIDLE 7 6 5 4 3 2 1 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE Management done interrupt masked. • RCOM Receive complete interrupt masked. • RBNA Receive buffer not available interrupt masked.
AT75C220 MAC PHY Maintenance Register Register Name: ETH_MAN Access Type: Read/write Reset Value: 0x0 31 30 LOW HIGH 23 22 29 28 21 PHYA 15 27 26 RW 25 20 19 18 17 REGA 14 13 24 PHYA 16 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA Writing to this register starts the shift register that controls the serial connection to the PHY.
MAC Hash Address High Register Name: ETH_HSH Access Type: Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Hash Address bits 63 to 32.
AT75C220 MAC Specific Address (1, 2, 3 and 4) High Register Name: ETH_SA1H,...ETH_SA4H Access Type: Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR Unicast Addresses (1, 2, 3 and 4), Bits 47:32. MAC Specific Address (1, 2, 3 and 4) Low Register Name: ETH_SA1L,...
MAC Statistics Register Block These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The statistics register block contains the registers found in Table 16. Table 16. Statistics Register Block Register Name Description ETH_FRA Frames transmitted OK. A 24-bit register counting the number of frames successfully transmitted. ETH_SCOL Single collision frames.
AT75C220 AIC: Advanced Interrupt Controller The AT75C220 integrates the Atmel advanced interrupt controller (AIC). For details on this peripheral, refer to the datasheet, literature number 1246. The interrupt controller is connected to the fast interrupt request (NFIQ) and the standard interrupt request (NIRQ) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input (FIQ).
Table 17. Interrupt Sources (Continued) Interrupt Source Interrupt Name 14 UARTB 15 PIOB 16 - 31 Reserved Interrupt Description USART B Interrupt PIO B Interrupt Priority Controller Interrupt Masking The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR.
AT75C220 4. The previous step establishes a connection to the corresponding ISR. This begins by saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note that the link register must be decrermented by 4 when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-assertion of the NIRQ to be taken into account by the core.
cleared during this phase in order to de-assert the NFIQ line. 6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by 4 (e.g., with instruction SUB PC, LR, #4). This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the SPSR and of masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The F bit in the SPSR is significant.
AT75C220 AIC User Interface Base Address: 0xFF030000 Table 18.
• SRCTYPE: Interrupt Source Type Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal sources. SRCTYPE Internal Sources External Sources 0 0 Level-sensitive Low-level sensitive 0 1 Edge-triggered Negative-edge triggered 1 0 Level-sensitive High-level sensitive 1 1 Edge-triggered Positive-edge triggered AIC Source Vector Registers Register Name: AIC_SVR0...
AT75C220 AIC FIQ Vector Register Register Name: AIC_FVR Access Type:Read-only Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQ The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ.
AIC Interrupt Pending Register Register Name: AIC_IPR Access Type:Read-only Reset Value: Undefined 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 PIOB USARTB MACB OAKA IRQ1(1) INT0 SPI MACA 7 6 5 4 3 2 1 0 PIOA TC2 TC1 TC0 USARTA SWI WDT FIQ Note: • 1. IRQ1 is available only in 256-lead PQFP package.
AT75C220 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type:Read-only Reset Value:0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active. • NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active.
AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type:Write-only Reset Value: Undefined • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active. • NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active.
AT75C220 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type:Write only Reset Value: Undefined • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active. • NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active.
AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type:Read/write Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIQV 23 22 21 20 SIQV 15 14 13 12 SIQV 7 6 5 4 SIQV • SIQV This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted.
AT75C220 PIO: Programmable I/O Controller The AT75C220 integrates 24 programmable I/O pins (PIO). Each pin can be programmed as an input or an output. Each pin can also generate an interrupt. The programmable I/O is implemented as two blocks, called PIO A and PIO B, 14 and 10 pins each, respectively. These pins are used for several functions: • external I/O for internal peripherals • keypad controller function • general-purpose I/O • visibility in test/debug mode, e.g.
Figure 14.
AT75C220 . Table 19.
PIO User Interface PIO Controller A Base Address: 0xFF00C000 PIO Controller B Base Address: 0xFF010000 Table 21.
AT75C220 PIO Enable Register Register Name:PIO_PER Access Type:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register is used to enable individual pins to be controlled by the PIO controller instead of the associated peripheral.
PIO Status Register Register Name:PIO_PSR Access Type:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled.
AT75C220 PIO Output Disable Register Register Name:PIO_ODR Access Type:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the information is stored.
PIO Set Output Data Register Register Name:PIO_SODR Access Type:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO.
AT75C220 PIO Output Data Status Register Register Name:PIO_ODSR Access Type:Read-only Reset Value:0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register shows the output data status which is programmed in PIO_SODR or PIO_CODR.
PIO Interrupt Enable Register Register Name:PIO_IER Access Type:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not.
AT75C220 PIO Interrupt Mask Register Register Name:PIO_IMR Access Type:Read-only Reset Value:0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR.
USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT75C220 provides two identical full-duplex, universal synchronous/asynchronous receiver/transmitters as USART A and USART B. These peripherals sit on the APB bus but are also connected to the ASB bus (and hence external memory) via a dedicated DMA.
AT75C220 Table 22. USART External Signals Signal Name Description NRTS Request to Send NCTS Clear to Send NDTR Data Terminal Ready NDSR Data Set Ready Input NDCD Data Carrier Detect Input NRI Note: Type Output Input Output Ring Indicator Input After a hardware reset, the USART SC and modem pins are not enabled by default (see “PIO: Programmable I/O Controller” on page 63).
Table 23. Clock Generator Table CD = 24 x 106/ 16 x baud rate Actual CD Actual Baud Rate (bps) Error (bps) % Error 38400 39.06 39 38461.5 61.5 0.16 57600 26.04 26 57692.3 92.3 0.16 Required Baud Rate (bps) 115200 13.02 13 115384.6 184.6 0.16 Notes: 1. CD = clock driver 2. For information on obtaining exact baud rates using the value of CD given above, the selected clock frequency must be 23,961,600 Hz (23.9616 MHz). Figure 16.
AT75C220 Receiver Asynchronous Receiver The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is 16 times the baud rate.
Time-out This function allows an idle condition on the RXD line to be detected. The maximum delay for which the USART should wait for a new character to arrive while the RXD line is inactive (high level) is programmed in US_RTOR. When this register is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set.
AT75C220 Figure 20. Synchronous and Asynchronous Mode: Character Transmission Example: 8-bit, parity enabled 1 stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Break A break condition is a low signal level which has a duration of at least one character, including start/stop bits and parity. Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR.
Interrupt Generation Each status bit in US_CSR has a corresponding bit in US_IER and US_IDR that controls the generation of interrupts by asserting the USART interrupt line connected to the AIC. US_IMR indicates the status of the corresponding bits. When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted. Figure 21.
AT75C220 Peripheral Data Controller Each USART channel is closely connected to a corresponding peripheral data controller channel. One is dedicated to the receiver, the other is dedicated to the transmitter. Note: The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR. The PDC channel is programmed using US_TPR and US_TCR for the transmitter and US_RPR and US_RCR for the receiver.
USART User Interface Base Address USART A: 0xFF018000 Base Address USART B: 0xFF01C000 Notes: 82 Offset Register Name 0x00 US_CR 0x04 Description Access Reset Value Control Register Write-only – US_MR Mode Register Read/write 0 0x08 US_IER Interrupt Enable Register Write-only – 0x0C US_IDR Interrupt Disable Register Write-only – 0x10 US_IMR Interrupt Mask Register Read-only 0 0x14 US_CSR Channel Status Register Read-only 0x18(1) 0x18 US_RHR Receiver Holding Register
AT75C220 USART Control Register Name: US_CR Access Type:Write-only Reset Value:Undefined • • • • • • • • • • • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SENDA STTTO STPBRK STTBRK RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset. RSTTX: Reset Transmitter 0 = No effect.
1 = In multi-drop mode only, the next character written to the US_THR is sent with the address bit set.
AT75C220 USART Mode Register Name: US_MR Access Type:Read/write Reset Value:0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – CLKO MODE9 – 14 13 12 11 10 9 15 CHMODE NBSTOP 7 6 5 CHRL • 8 SYNC 3 2 1 0 – – – – USCLKS: Clock Selection (Baud Rate Generator Input Clock) Selected Clock 0 0 ACLK 0 1 ACLK/8 1 X External (SCK) CHRL: Character Length Start, stop and parity bits are added to the character length.
• NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC. NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved • CHMODE: Channel Mode CHMODE • Mode Description 0 0 Normal Mode The USART channel operates as an Rx/Tx USART. 0 1 Automatic Echo Receiver data input is connected to TXD pin.
AT75C220 USART Interrupt Enable Register Name: US_IER Access Type:Write-only Reset Value: Undefined • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – DMSI TXEMPTY TIMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY: Enable RXRDY Interrupt 0 = No effect. 1 = Enables RXRDY interrupt. • TXRDY: Enable TXRDY Interrupt 0 = No effect.
USART Interrupt Disable Register Name: US_IDR Access Type:Write-only Reset Value: Undefined • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – DMSI TXEMPTY TIMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY: Disable RXRDY Interrupt 0 = No effect. 1 = Disables RXRDY interrupt. • TXRDY: Disable TXRDY Interrupt 0 = No effect. 1 = Disables TXRDY interrupt.
AT75C220 USART Interrupt Mask Register Name: US_IMR Access Type:Read-only Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – DMSI TXEMPTY TIMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY: RXRDY Interrupt Mask 0 = RXRDY interrupt is disabled. 1 = RXRDY interrupt is enabled. • TXRDY: TXRDY Interrupt Mask 0 = TXRDY interrupt is disabled.
USART Channel Status Register Name: US_CSR Access Type:Read-only Reset Value: 0x18 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – DMSI TXEMPTY TIMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
AT75C220 • TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and break is not active. Equal to zero when the USART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one. • DMSI: Delta Modem Status Indication Interrupt 0 = No effect.
USART Baud Rate Generator Register Name: US_BRGR Access Type:Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD • CD: Clock Divisor This register has no effect if synchronous mode is selected with an external clock.
AT75C220 USART Receiver Time-out Register Name: US_RTOR Access Type:Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TO • TO: Time-out Value When a value is written to this register, a start time-out command is automatically performed. TO 0 1 - 255 Effect Disables the RX time-out function.
USART Transmitter Time-guard Register Name: US_TTGR Access Type:Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TG • TG: Time-guard Value TG 0 1 - 255 Effect Disables the TX time-guard function.
AT75C220 USART Receive Counter Register Name: US_RCR Access Type:Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0: Stop peripheral data transfer dedicated to the receiver.
USART Transmit Counter Register Name: US_TCR Access Type:Read/write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop peripheral data transfer dedicated to the transmitter. 1 - 65535: Start peripheral data transfer if TXRDY is active.
AT75C220 Modem Control Register Register Name:US_MC Access Type:Write-only Reset Value: Undefined 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – FCM – – – RTS DTR This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Control Register are indicated below.
Modem Status Register Register Name:US_MS Access Type:Read-only Reset Value:Undefined 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – FCMS 7 6 5 4 3 2 1 0 DCD RI DSR CTS DDCD TERI DDSR DCTS This register provides the current state of the control lines from the modem (or peripheral device) to the CPU.
AT75C220 TC: Timer/Counter The AT75C220 features a timer/counter block which includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user.
Signal Name Description Channel Signal Description Type XC0, XC1, XC2 External clock inputs I TIOA Capture mode: General-purpose input Waveform mode: General-purpose output I O TIOB Capture mode: General-purpose input Waveform mode: General-purpose input/output I O INT Interrupt signal output O SYNC Synchronization input signal I TCLK0, TCLK1, TCLK2 External clock inputs I TIOA0 TIOA signal for Channel 0 I/O TIOB0 TIOB signal for Channel 0 I/O TIOA1 TIOA signal for Channel 1 I/O
AT75C220 Figure 23. Clock Selection Figure 24. Clock Control Selected Clock CLKS Trigger CLKI ACLK/2 ACLK/8 CLKSTA ACLK/32 ACLK/128 CLKEN CLKDIS Selected Clock ACLK/1024 XC0 Q XC1 XC2 Q S S R R BURST 1 Counter Clock Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. 1. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register.
Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 25 shows the configuration of the TC Channel when programmed in capture mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers.
Figure 25.
Waveform Operating Mode This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform operating mode allows the TC channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles or to generate different types of one-shot or repetitive pulses. In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an external event (EEVT parameter in TC_CMR).
CLKSTA ACLK/2 CLKEN CLKDIS ACPC CLKI ACLK/8 Q S ACLK/128 CPCDIS ACLK/1024 Q XC0 R S ACPA R XC1 XC2 CPCSTOP AEEVT MTIOA Output Controller ACLK/32 Figure 26.
TC User Interface TC Base Address: 0xFF014000 Table 24. TC Global Memory Map Offset Register Name Channel/Register Access Reset Value 0x00 See Table 25 TC Channel 0 See Table 25 0x40 See Table 25 TC Channel 1 See Table 25 0x80 See Table 25 TC Channel 2 See Table 25 0xC0 TC_BCR TC Block Control Register Write-only – 0xC4 TC_BMR TC Block Mode Register Read/write 0 TC_BCR and TC_BMR control the TC block. TC channels are controlled by the registers listed in Table 25.
AT75C220 TC Block Control Register Register Name:TC_BCR Access Type:Write-only • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
TC Block Mode Register Register Name:TC_BMR Access Type:Read/write Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 – – TC0XC0S: External Clock Signal 0 Selection TC0XC0S • Signal Connected to XC0 0 0 TCLK0 0 1 None 1 0 TIOA1 1 1 TIOA2 TC1XC1S: External Clock Signal 1 Selection TC1XC1S • TC2XC2S Signal Connected to XC1 0 0 TCLK1
AT75C220 TC Channel Control Register Register Name:TC_CCR Access Type:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. 1 = Disables the clock.
TC Channel Mode Register: Capture Mode Register Name:TC_CMR Access Type:Read/write Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 13 12 11 10 WAVE CPCTRG – – – ABETRG 7 6 5 3 2 LDBDIS LDBSTOP TCCLKS: Clock Selection TCCLKS • 4 BURST Clock Selected 0 0 0 ACLK/2 0 0 1 ACLK/8 0 1 0 ACLK/32 0 1 1 ACLK/128 1 0 0 ACLK/1024 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 CLKI: Clock Invert 0 = Counter i
AT75C220 • • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 None 0 1 Rising edge 1 0 Falling edge 1 1 Each edge ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture mode is enabled.
TC Channel Mode Register: Waveform Mode Register Name:TC_CMR Access Type:Read/write Reset Value: 0x0 31 30 29 BSWTRG 23 22 • 20 14 13 12 CPCTRG – ENETRG 7 6 5 CPCDIS CPCSTOP 4 BURST TCCLKS: Clock Selection Clock Selected 0 0 ACLK/2 0 0 1 ACLK/8 0 1 0 ACLK/32 0 1 1 ACLK/128 1 0 0 ACLK/1024 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.
AT75C220 • • EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 None 0 1 Rising edge 1 0 Falling edge 1 1 Each edge EEVT: External Event Selection EEVT TIOB Direction 0 0 TIOB Input(1) 0 1 XC0 Output 1 0 XC1 Output 1 1 XC2 Output Note: • Signal Selected as External Event 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
• AEEVT: External Event Effect on TIOA AEEVT • • Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle BCPB: RB Compare Effect on TIOB BCPB • Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle BCPC: RC Compare Effect on TIOB BCPC • Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Tog
AT75C220 • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle TC Counter Value Register Register Name:TC_CVR Access Type:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real-time.
TC Register A Register Name:TC_RA Access Type:Read-only if WAVE = 0, Read/write if WAVE = 1 Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real-time.
AT75C220 TC Status Register Register Name:TC_SR Access Type:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register.
TC Interrupt Enable Register Register Name:TC_IER Access Type:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the counter overflow interrupt. 1: Enables the load overrun interrupt.
AT75C220 TC Interrupt Disable Register Register Name:TC_IDR Access Type:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the counter overflow interrupt. 1 = Disables the load overrun interrupt if WAVE = 0.
TC Interrupt Mask Register Register Name:TC_IMR Access Type:Read-only Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0 = The counter overflow interrupt is disabled. 1 = The counter overflow interrupt is enabled.
AT75C220 SPI: Serial Peripheral Interface The AT75C220 integrates a serial peripheral interface (SPI) that provides communication with external devices in master or slave mode. Typically it is used to connect to external processors or serial Flash. Figure 27. Serial Peripheral Interface Block Diagram ACLK Serial Peripheral Interface MISO MISO MOSI MOSI SPCK SPCK ACLK/32 APB INT NPCSS NPCSS NPCS1 NPCS1 NPCS2 NPCS2 NPCS3 NPCS3 Advanced Interrupt Controller Table 26.
Master Mode In master mode, the SPI controls data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the ARM core writes to the SP_TDR. For details on the SPI memory map, refer to Table 27 on page 127. Transmit and receive buffers maintain the data flow at a constant rate with a reduced requirement for high-priority interrupt servicing.
AT75C220 Figure 28.
Figure 29.
AT75C220 Slave Mode In slave mode, the SPI waits for NPCSS to go active low before receiving the serial clock from an external master. CPOL, NCPHA and BITS fields of SP_CSR0 are used to define the transfer characteristics. The other chip select registers are not used in slave mode. Figure 30.
Data Transfer Figure 31, Figure 32 and Figure 33 show examples of data transfers. Figure 31. SPI Transfer Format (NPCHA Equals One, Eight Bits per Transfer) 1 SPCK Cycle (for reference) 2 3 5 4 6 8 7 SPCK (CPOL=0) SPCK (CPOL=1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB X NPCSS (to slave) Figure 32.
AT75C220 Figure 33. Programmable Delays (DLYBCS, DLYBS and DLTBCT) Chip Select 1 Change peripheral Chip Select 2 No change of peripheral SPCK Output DLYBCS DLYBS Clock Generation In master mode, the SPI master clock is either ACLK or ACLK/32, as defined by the MCK32 field of SP_MR. The SPI baud rate clock is generated by dividing the SPI master clock by a value between 4 and 510. The divisor is defined in the SCBR field in each chip select register.
Table 27.
AT75C220 SPI Mode Register Register Name:SP_MR Access Type:Read/write Reset Value:0x0 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS • 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 LLB – – – MCK32 PCSDEC PS MSTR PCS MSTR: Master/Slave Mode 0 = SPI is in slave mode. 1 = SPI is in master mode. MSTR configures the SPI interface for either master or slave mode operation.
• PCS: Peripheral Chip Select This field is only used if fixed peripheral select is active (PS=0). If PCSDEC=0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC=1: NPCS[3:0] output signals = PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
AT75C220 SPI Transmit Data Register Register Name:SP_TDR Access Type:Write-only Reset Value:– 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data that is to be transmitted by the SPI interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
SPI Status Register Register Name: SP_SR Access Type: Read-only Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – SPIENS 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – SPENDRX SPENDTX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full 0 = No data has been received since the last read of SP_RDR.
AT75C220 SPI Interrupt Enable Register Register Name:SP_IER Access Type:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Enable 0 = No effect. • TDRE: SPI Transmit Data Register Empty Interrupt Enable 0 = No effect. 1 = Enables the receiver data register full interrupt.
SPI Interrupt Disable Register Register Name:SP_IDR Access Type:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Disable 0 = No effect. • TDRE: Transmit Data Register Empty Interrupt Disable 0 = No effect. 1 = Disables the receiver data register full interrupt.
AT75C220 SPI Interrupt Mask Register Register Name:SP_IMR Access Type:Read-only Reset Value: 0x0 • 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF RDRF: Receive Data Register Full Interrupt Mask 0 = Receive data register full interrupt is disabled. 1 = Receive data register full interrupt is enabled.
SPI Receive Pointer Register Register Name:SP_RPR Access Type:Read/write Reset Value:0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer.
AT75C220 SPI Transmit Pointer Register Register Name:SP_TPR Access Type:Read/write Reset Value:0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Pointer Register TXPTR must be loaded with the address of the transmit buffer.
SPI Chip Select Register Register Name:SP_CSR0 Access Type:Read/write Reset Value:0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – – NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
AT75C220 • SCBR: Serial Clock Baud Rate In master mode, the SPI interface uses a modulus counter to derive the SPCK baud rate from the SPI master clock (selected between ACLK and ACLK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR.
WD: Watchdog Timer The AT75C220 has an internal watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation, the user reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the watchdog timer generates one or a combination of the following signals depending on the parameters in WD_OMR: • If RSTEN is set, an internal reset is generated (WD_RESET as shown in Figure 34).
AT75C220 WD Overflow Mode Register Name: WD_OMR Access: Read/write Reset Value:0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 OKEY 7 6 5 4 OKEY • 3 2 1 0 EXTEN IRQEN RSTEN WDEN WDEN: Watchdog Enable 0 = Watchdog is disabled and does not generate any signals. 1 = Watchdog is enabled and generates enabled signals.
WD Clock Mode Register Name: WD_CMR Access: Read/write Reset Value:0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 CKEY • 7 6 CKEY – 5 4 HPCV 0 WDCLKS WDCLKS: Clock Selection WDCLKS Clock Selected 0 0 ACLK/8 0 1 ACLK/32 1 0 ACLK/128 1 1 ACLK/1024 • HPCV: High Preload Counter Value Counter is preloaded when watchdog counter is restarted with bits 0 to 11 set (FFF) and bits 12 to 15
AT75C220 WD Status Register Name: Access: WD_SR Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – WDOVF • WDOVF: Watchdog Overflow 0 = No watchdog overflow. 1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset.
Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg.
