User Manual

AT75C220
106
TC User Interface
TC Base Address: 0xFF014000
TC_BCR and TC_BMR control the TC block. TC channels are controlled by the registers listed in Table 25. The offset of
each of the channel registers in Table 25 is in relation to the offset of the corresponding channel as stated in Table 24.
Note: 1. Read only if WAVE = 0
Table 24. TC Global Memory Map
Offset Register Name Channel/Register Access Reset Value
0x00 See Table 25 TC Channel 0 See Table 25
0x40 See Table 25 TC Channel 1 See Table 25
0x80 See Table 25 TC Channel 2 See Table 25
0xC0 TC_BCR TC Block Control Register Write-only –
0xC4 TC_BMR TC Block Mode Register Read/write 0
Table 25. TC Channel Memory Map
Offset Register Name Description Access Reset Value
0x00 TC_CCR Channel Control Register Write-only –
0x04 TC_CMR Channel Mode Register Read/write 0
0x08 Reserved –
0x0C Reserved –
0x10 TC_CVR Counter Value Register Read/write 0
0x14 TC_RA Register A Read/write
(1)
0
0x18 TC_RB Register B Read/write
(1)
0
0x1C TC_RC Register C Read/write 0
0x20 TC_SR Status Register Read-only –
0x24 TC_IER Interrupt Enable Register Write-only –
0x28 TC_IDR Interrupt Disable Register Write-only –
0x2C TC_IMR Interrupt Mask Register Read-only 0