User Manual

AT75C220
138
SPI Chip Select Register
Register Name:SP_CSR0
Access Type:Read/write
Reset Value:0x0
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a
desired clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA
is used with CPOL to produce a desired clock/data relationship between master and slave devices.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS ––NCPHA CPOL
BITS[3:0]
Bits per
Transfer BITS[3:0]
Bits per
Transfer
0000 8 1000 16
0001 9 1001 Reserved
0010 10 1010 Reserved
0011 11 1011 Reserved
0100 12 1100 Reserved
0101 13 1101 Reserved
0110 14 1110 Reserved
0111 15 1111 Reserved