User Manual

AT75C220
24
SDMC: SDRAM Controller
The AT75C220 integrates an SDRAM controller (SDMC).
The ARM accesses external SDRAM by means of the
SDRAM memory controller.
The SDMC shares the same address and data pins as the
static memory controller but has separate control signals.
The SDMC interface is a memory-mapped APB slave.
For very low frequency selection in low power mode, the
SDRAM should be refreshed frequently.
Main features of the SDMC are:
• External memory mapping
• Up to 4 chip select lines
• 32- or 16-bit data bus
• Byte write or byte select lines
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
• Programmable burst mode
The signals RAS, CAS, WE, A[21:0], and D[15:0] have
functions similar to those of a conventional DRAM.
DCLK is the free-running, normally continuous clock to
which all other signals are synchronized; CKE is an enable
signal that gates the other control inputs. Note that CKE is
not bonded out since it is always active high.
APB Interface
The SDMC interface is a memory-mapped APB slave.
ASB Interface
The SDMC is also an ASB slave and has a reserved mem-
ory region in the ASB memory map.
Read and Write Bursts
The SDMC has been modified so read accesses are per-
formed in bursts of four for accesses to 32-bit memory or
bursts of eight for 32-bit access to 16-bit memory. Read
accesses are performed as shown in Figure 8, Figure 9
and Figure 10. Note that read bursts are terminated if a
non-sequential access is detected. However, pipelined
commands from the SDRAM may be still be executed but
the resultant read data is ignored.
Three separate read accesses are shown in Figure 8, Fig-
ure 9 and Figure 10. In Figure 8, the data from all four
reads is used, in Figure 9 the data from the last two reads
is discarded. Figure 10 shows a single non-sequential
access to a new row.
Table 10. External Memory Interface
Signal Name Type Description
DCLK Output SDRAM Clock
A[21:0] Output Memory address (Shared with SMC)
D[15:0] Input Memory data input (Shared with SMC)
DQM[1:0] Output SDRAM byte masks
CS0 Output SDRAM chip select, active low
CS1 Output SDRAM chip select, active high
WE Output SDRAM write enable, active low
RAS Output Row Address Select, active low
CAS Output Column Address Select, active low