User Manual

AT75C220
39
• BIG
Receive 1522 bytes. When set, the MAC will receive up to 1522 bytes. Normally the MAC will receive frames up to
1518 bytes in length.
• EAE
External address match enable. Optional.
• CLK
The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). For conformance with IEEE 802.3
MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
• RTY
Retry test. When set, the time between frames will always be one time slot. For test purposes only. Must be cleared for
normal operation.
MAC Network Status Register
Register Name: ETH_SR
Access Type: Read-only
Reset Value: 0x4
• LINK
The status of the LINK pin. Optional.
• MDIO
Returns status of the MDIO pin.
• IDLE
The PHY management logic is idle (i.e., has completed).
CLK MDC
00 HCLK divided by 8
01 HCLK divided by 16
10 HCLK divided by 32
11 HCLK divided by 64
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
–––––IDLE MDIO LINK