User Manual

AT75C220

PIO User Interface

PIO Controller A Base Address: 0xFF00C000

PIO Controller B Base Address: 0xFF010000

Notes: 1. The reset value of this register depends on the level of the external pins at reset.

2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have

occurred on any pins between the reset and the read.

Table 21. PIO Controller Memory Map

Offset Register Name Description Access Reset Value

0x00 PIO_PER PIO Enable Register Write-only –

0x04 PIO_PDR PIO Disable Register Write-only –

0x08 PIO_PSR PIO Status Register Read-only –

0x0C – Reserved ––

0x10 PIO_OER Output Enable Register Write-only –

0x14 PIO_ODR Output Disable Register Write-only –

0x18 PIO_OSR Output Status Register Read-only 0x0

0x1C – Reserved ––

0x20 – Reserved ––

0x24 – Reserved ––

0x28 – Reserved – 0x0

0x2C – Reserved ––

0x30 PIO_SODR Set Output Data Register Write-only –

0x34 PIO_CODR Clear Output Data Register Write-only –

0x38 PIO_ODSR Output Data Status Register Read-only 0x0

0x3C PIO_PDSR Pin Data Status Register Read-only See Note 1

0x40 PIO_IER Interrupt Enable Register Write-only –

0x44 PIO_IDR Interrupt Disable Register Write-only –

0x48 PIO_IMR Interrupt Mask Register Read-only –

0x4C PIO_ISR Interrupt Status Register Read-only See Note 2