User Manual

AT75C220

Modem Status Register

Access Type:Read-only

Reset Value:Undefined

This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to

this current-state information, four bits of the Modem Status Register provide change information. These bits are set to a

logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the

Modem Status Register.

• DCTS: Delta Clear to Send

Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU.

• DDSR: Delta Data Set Ready

Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU.

• TERI: Trailing Edge Ring Indicator

Bit 2 indicates that the NRI input to the chip has changed from a low to a high state.

• DDCD: Delta Data Carrier Detect

Bit 3 indicates that the NDCD input has changed state.

Note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. This is reflected in the modem

status register.

• CTS: Clear to Send

This bit is the complement of the Clear to Send (NCTS) input.

• DSR: Data Set Ready

This bit is the complement of the Data Set Ready (NDSR) input.

• RI: Ring Indicator

This bit is the complement of the Ring Indicator (NRI) input.

• DCD: Data Carrier Detect

This bit is the complement of the Data Carrier Detect (NDCD) input.

• FCMS: Flow Control Status

This bit indicates the value of the FCM in the US_MC.

31 30 29 28 27 26 25 24

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23 22 21 20 19 18 17 16

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15 14 13 12 11 10 9 8

–––––––FCMS

76543210

DCD RI DSR CTS DDCD TERI DDSR DCTS