Features • Implements Bluetooth™ Specification on Short Distance Wireless Communication in 2.
Overview The AT76C551 is a single chip controller providing the functionality for high data rate, short distance wireless communications in the free ISM band. In conjunction with a 2.4 GHz transceiver, it provides a cost effective networking solution for a wide range of digital communication devices and computer peripherals.
AT76C551 Typical AT76C551 Home Application Fax AT76C551 Bluetooth Adapter RS-232 RS-232 AT76C551 Bluetooth Adapter Printer AT76C551 Bluetooth Adapter PCMCIA USB AT76C551 Bluetooth Adapter USB AT76C551 Bluetooth Adapter Keyboard Laptop Computer AT76C551 Powered Mouse Typical AT76C551 Mobile Application Pen Computer AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter RS-232 AT76C551 Bluetooth Adapter USB USB AT76C551 Bluetooth Adapter Monitor Tower Box RS-232 Printer AT76C551 Powered Cell
Functional Diagram Register Bank TxSync RxFrontEnd D.P.RAM ARM 64K Bytes D.P.RAM BT 64K Bytes D.P.RAM Controller RSSI ADC 64K Bytes D.P.RAM ASB 1K Byte D.P.RAM USB 32K Bytes D.P.RAM UART 32K Bytes D.P.RAM 32K Bytes D.P.
AT76C551 Pinout and Package Options The AT76C551 controller will be available in three different packages, each will have the same basic functionality but with a different system interface (PCMCIA 8-bit, full-speed USB, extended speed RS-232). The prototype version comes in a LQFP-176 package and supports the three different interfaces simultaneously.
Pin Summary – Pin Assignment in Numerical Order Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type 1 VCC Digital Supply 38 AGND Analog Ground 75 MEM_DATA5 B 2 EXT_13_MHz I 39 RSSI I 76 MEM_DATA4 B 3 EXT_13_MHz_OUT O 40 AVCC 77 MEM_DATA3 B 4 GND Digital Ground 41 VC_IN LOG 1 78 MEM_DATA2 B 5 EXT_OSC I 42 AGND Analog Ground 79 MEM_DATA1 B 6 GND Digital Ground 43 VC_OUT LOG O 80 MEM_DATA0 B 7 TC_ENABL O 44 AVCC 81 GND Digital Ground
AT76C551 Pin Summary – Pin Assignment in Numerical Order (Continued) Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type 112 U_CD_ I 134 GND Digital Ground 156 DB_CLK O 113 VCC Digital Supply 135 PC_D7 B 157 VCC Digital Supply 114 DP B 136 PC_D6 B 158 NTRST I 115 DM B 137 PC_D5 B 159 TCK I 116 GND Digital Ground 138 PC_D4 B 160 TDI I 117 P_OR_UN I 139 PC_D3 B 161 TMS I 118 PC_A14 I 140 PC_D2 B 162 TDO I 119 PC_A13 I 141 PC_D
Pin Summary – Pin Assignment in Alphabetical Order Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type 49 ABCLK O 81 GND Digital Ground 67 MEM_DATAH3 B 53 ABCLK_IN I 95 GND Digital Ground 66 MEM_DATAH4 B 48 ACLK O 109 GND Digital Ground 65 MEM_DATAH5 B 52 ACLK_IN I 163 GND Digital Ground 64 MEM_DATAH6 B 46 ADI I 171 GND Digital Ground 63 MEM_DATAH7 B 45 ADO O 173 GND Digital Ground 146 NCE 38 AGND Analog Ground 172 LFT 147 NCE1 I
AT76C551 Pin Summary – Pin Assignment in Alphabetical Order (Continued) Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type 140 PC_D2 B 9 TC_CLK O 107 U_RI_ I 139 PC_D3 B 8 TC_DATA O 104 U_RTS_ O 138 PC_D4 B 7 TC_ENABL O 111 USART_RX I 137 PC_D5 B 16 TC_I_CP_SW O 106 USART_TX O 136 PC_D6 B 19 TC_LD I 41 VC_IN LOG 1 135 PC_D7 B 13 TC_PUPLL O 43 VC_OUT LOG O 169 PC_RESET I 17 TC_PUREG O 1 VCC Digital Supply 170 PLL_TEST_PIN I 1
Signal Description – Pin Name Order I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Type Pin Name Description Supply Pins AGND Power Analog Ground AVCC Power Analog Supply GND Power Digital Ground VCC Power Digital Supply Global Pin PC_RESET I Global Reset pin XTAL1 I Crystal oscillator input XATL2 O Crystal oscillator output EXT_13_MHZ I 13 MHz input clock EXT_13_MHZ_OUT O 13 MHz output clock EXT_OSC I External oscillator input
AT76C551 Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description Baseband Interface Pins TC_CLK O Clock output for transceiver control bus TC_DATA O Data output for transceiver control bus TC_ENBL O Enable output for transceiver control bus TC_LD I Lock detect input TC_PU_REG O Transceiver voltage regulator power up TC_PU_PLL O Power up output for transceiver PLL TC_PU_VCO O V
Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Type Pin Name Description NIORD I I/O Read – Asserted by the host system to indicate to BT that a read from the I/O address space is required. The chip will not respond until it has been configured for I/O operation by the system. NIOWR I I/O Write – Asserted by the host system to indicate to the chip that a write to its I/O address space is required.
AT76C551 Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description ASYNC O Frame Sync – Out ACLK_IN I Master Clock – In ABCLK_IN I Bit Clock – In ASYNC_IN I Frame Sync – In DB_DATA O Debug data port DB_CLK O Debug clock port NTRST I JTAG reset input TCK I JATG clock TDI I JTAG data input TDO I JTAG data output TMS I JTAG master select input TEST_CTRL I For product
Functional Description – Pin Name Order Name Type Description AGND Power Analog Ground – used by the RSSI ADC, the Voice CODEC ADC and DAC AVCC Power Analog Supply – used by the RSSI ADC, the Voice CODEC ADC and DAC GND Power Digital Ground VCC Power Digital Supply Supply Pins Global Pin PC_RESET I Global Reset Pin XTAL1 I Crystal oscillator input XATL2 O Crystal oscillator output EXT_13_MHZ I 13 MHz input clock EXT_13_MHZ_OUT O 13 MHz output clock EXT_OSC I External oscilla
AT76C551 Functional Description – Pin Name Order (Continued) Name Type Description Baseband Interface Pins TC_CLK O Clock output for transceiver control bus TC_DATA O Data output for transceiver control bus TC_ENBL O Enable output for transceiver control bus TC_LD I Lock detect input TC_PUREG O Transceiver voltage regulator power up TC_PUPLL O Power up output for transceiver PLL TC_PUVCO O VCO power up output TC_PURXTX O Power up output for Transmit/Receive sections of transceiver
Functional Description – Pin Name Order (Continued) Name Type Description NIOWR I I/O Write – Asserted by the host system to indicate to the chip that a write to its I/O address space is required. The device will not respond until it has been configured for I/O operation by the system. NREG I Attribute Memory Select – Driven by the host to select between Attribute memory or I/O space (REG asserted) and Common memory (REG deasserted) in the device and the PCMCIA card.
AT76C551 Functional Description – Pin Name Order (Continued) Name Type Description JTAG Pins DB_DATA O Debug data port DB_CLK O Debug clock port NTRST I JTAG reset input TCK I JATG clock TDI I JTAG data input TDO I JTAG data output TMS I JTAG master select input TEST_CTRL I For production test TEST_ECK I For production test PLL_TEST_PIN I For production test TEST Pins Internal Architecture The AT76C551 chip is based on the ARM7TDMI processor.
The memory interface supports two ports for efficient use of the memory unit. Each port provides access to all memories independently of the other. A round-robin priority scheme is used when both ports require access to the same memory. One port is dedicated to the ARM interface while the other can be used by either the PCMCIA interface or the USB interface. The selection is determined by the PC_OR_UN pin. PCMCIA Interface Unit The PCMCIA interface unit implements a PCMCIA 2.1/JEIDA 4.
AT76C551 Encryption/ Decrytion Encryption and decryption is provided with the use of a secret key. Encryption and decryption are carried out on-the-fly with minimal intervention from the processor. The encryption/decryption data are interchanged between the other Bluetooth low-level processing modules automatically. Authentication Processing Accelerator Processing-intensive authentication procedures are implemented in the hardware which reduce the time for authentication key production.
Voice CODEC The voice CODEC module supports both CVSD (Continuous Variable Slope Delta) coding and log PCM coding (A-law and U-law). The coded voice data from both coding algorithms will be transferred with a constant bit rate of 64 kbits/sec.
AT76C551 Table 1. Need Table Caption Baud Rate Divisor Used % Error Between Desired and Actual 1200 5000 0 2400 2500 0 4800 1250 0 9600 625 0 19.2K 312 0.16 38.4K 156 0.16 57.6K 104 0.16 115.2K 52 0.16 230.4K 26 0.16 460.8K 13 0.16 921.6K 6.5 0.16 The UART module provides serial asynchronous receive data synchronization, parallel-toserial and serial-to-parallel data conversions for both the transmitter and receiver sections.
Figure 1.
AT76C551 Register Description Memory Controller Register Set The Memory Controller Register Set can be configured to cooperate with various types of external Flash and SRAM memories. The configuration parameters are held by Memory Configuration Registers (MCR) which are mapped into AMBA™ memory space. After AT76C551 resets, MCR default values guarantee correct operation of external Flash or SRAM memories connected to AT76C551.
PCMCIA Configuration Registers The PCMCIA configuration registers are required by the PCMCIA standard. These registers are mapped into PCMCIA attribute memory space to allow the host to configure basic parameters of the PCMCIA device. They are accessible by the host but they are not accessible by ARM core.
AT76C551 • Bit 6 – CORES: Core Reset While this bit is set, AT76C551 units on the AMBA bus (including ARM core) are held in reset state. When this bit is cleared, AT76C551 units on the AMBA bus exit reset state and ARM core, in particular, begins code execution by fetching its reset exception vector. Note: This bit is not automatically cleared after it is set. • Bit 5 – 16/8-bit: 16/8-bit Access Mode If set, enables the 16-bit access of PCMCIA module with the system memory.
SIR3 – AMBA AHSR: Address High Select Register PCMCIA addr: 0003 hex R/W 8 bits • Bit 7 – Reserved • Bits 6..0 – AD[14:8] This register is used by the host in conjunction with SIR1, SIR2, SIR4 and SIR5 in order to access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA interface unit. Each time SIR4 is accessed, the AMBA AHSR drives AMBA address lines 14..8. Note: Default Value: 00 he SIR4 – AMBA I/O DLR: Data Low Register PCMCIA addr: 0004 hex R/W 8 bits • Bits 7..
AT76C551 • SIR6 – GPR1: General Purpose Register 1 GPR1 PCMCIA addr: 0006 hex W 8 bits • Bits 7..0 – GPR1[7:0] The host can only write GPR1. GPR1 bits 7..0 are reflected to bits 7..0 of MIR4 so theARM core can read them. Note: Default Value: 00 hex SIR7 – GPR2: General Purpose Register 2 PCMCIA addr: 0007 hex 8 bits • Bits 7..0 – GPR2[7:0] The host can only write GPR2. GPR2 bits 7..0 are reflected to bits 15..8 of MIR4 so the ARM core can read them.
SIR12 – MR4: Mirror Register 4 PCMCIA addr: 0011 hex R 8 bits • Bits 7..0 – MR4[7:0] Note: Default Value: 00 hex – The host can only read MR4. MR4 bits 7..0 reflect bits 15..8 of MIR1, which can be written by the ARM core. SIR13 – MR5: Mirror Register 5 PCMCIA addr: 0012 hex R 8 bits • Bits 7..0 – MR5[7:0] The host can only read MR5. MR5 bits 7..0 reflect bits 7..0 of MIR2, which can be written by the ARM core.
AT76C551 MAC Interface Registers MAC Interface Registers (MIR) lie in the PCMCIA interface unit. They are mapped into AMBA memory space, i.e. they are directly accessible by the ARM core but they are not directly accessible by the host. MIRs allow AT76C551 firmware to communicate with the host and to generate interrupts to the host processor. MIR0 – PIR1: Processor Interface Register 1 addr: 800000 hex R/W 16 bits • Bits 15..4 – PIR1[15:4] General purpose I/O Bits 15..8 are reflected to bits 7..
MIR3 – PIR4: Processor Interface Register 4 addr: 80000C hex R/W 16 bits • Bits 15..8 – PIR4[15:8] General purpose I/O MIR3 bits 15..8 are reflected to bits 7..0 of MR8 so that the host can read them. • Bits 7..0 – PIR4[7:0] General purpose I/O MIR3 bits 7..0 are reflected to bits 7..0 of MR7 so that the host can read them. Note: Default Value: 0000 hex MIR0 – MIR3 provide a means of one-way communication from AT76C551 firmware to the host driver software.
AT76C551 Bluetooth Baseband Register Set Bluetooth Baseband processor register file is mapped to the AMBA address space. Table 3 summarizes Bluetooth Baseband registers, grouped in functional sections. Table 3. Bluetooth Register Set Register Addr. (hex) Function Packet Processing Address0 600000 Sets ADDR field used is various processes Address1 600004 Access code, packet encoding, encryption, etc.
Table 3. Bluetooth Register Set (Continued) Register Addr.
AT76C551 Address0 addr: 600000 hex R/W 32 bits • Bits 31..0 – ADDR[31:0] Sets ADDR field, used in access code generation, packet encoding, encryption and frequency hopping. Note: Default Value: 00000000 hex Address1 addr: 600004 hex R/W 32 bits • Bits 15..0 – ADDR[47:32] Sets ADDR field, used in access code generation, packet encoding, encoding and frequency hopping. • Bits 31..16 – Reserved Note: Default Value: 00000000 hex Pgrsp_counter addr: 600008 hex R/W 32 bits • Bits 31..
RSSI_CtrlStatus addr: 600014 hex R/W 32 bits • Bits 31..16 – Reserved • Bits 15..8 R – ADC data Result of last conversion (last RSSI value sampled) • Bit 7 – R ADC Status Set by hardware when conversion procedure has been completed • Bits 6..4 – Reserved • Bits 3..2 W – ADC Mode 00: ADC idle 01: One shot conversion 10: Continuous conversion • Bit 1 – W ADC Start Set by firmware to start a conversion procedure when ADC mode is “one shot conversion” (auto-clear).
AT76C551 • Bit 16 R – TxDataBusy Set by hardware while TX data is being streamed out • Bit 15 R – RxDataBusy Set by hardware while RX data is being streamed in • Bits 14...
• Bits 27..0 – CLKN[27:0] Provides native clock current value to firmware. Note: Default Value: 00000000 hex CLOCK addr: 600024 hex R/W 32 bits • Bits 31..28 – Reserved • Bits 27..0 – CLOCK[27:0] In this register specific fields of device’s native clock or of transmitter’s estimated in receiver native clock are set. Note: Default Value: 00000000 hex CLKPhase addr: 600028 hex R/W 32 bits • Bits 31..15 – Reserved • Bits 14..0 – CLKPhase[14:0] Provides native clock phase current value to firmware.
AT76C551 CLKCtrl addr: 600038 hex R/W 32 bits • Bits 31..4 – Reserved • Bit 3 – cmpCLKN0_invert 0: Native clock bit 0 is not inverted for timer comparisons. 1: Native clock bit 0 is inverted for timer comparisons. Bit 3 value is “don’t care” if bit 0 of the register is reset. • Bit 2 – ForcePhase_, Adjust Set by firmware to force native clock phase adjustment, i.e. set native clock phase equal to CLKPhaseCorrelCorrect register contents. Auto-clear.
RxTxSettleTimes addr: 600044 hex R/W 32 bits • Bits 31..24 – Reserved • Bits 23..16 – TC_TXON, settleTime[7:0] Microseconds from TC_TXON rise to outgoing packet data transmission. • Bits 15..8 – TC_RXON, settleTime[7:0] Microseconds from TC_RXON rise to correlator activation. • Bits 7..0 – TC_PURX/TX, settleTime[7:0] Microseconds from TC_PURX/TX rise to TC_TXON or TC_RXON rise. Note: Default Value: 00000000 hex TcCtrlStatus addr: 600048 hex R/W 32 bits • Bits 31..
AT76C551 • Bit 1 – TxEnable Set by firmware to start a RX cycle at then next event generated by compare timer CmpTimer_RxTxStart. • Bit 0 – RxTx_, Abort Set by firmware to immediately abort current RX or TX cycle, or to cancel the programmed RX or TX cycle due to start. Note: Default Value: 00000000 hex Provided that bit 1 of TcCtrlStatus register is set the Bluetooth baseband processor has the ability to automatically generate the sequence of signals necessary to implement TX and RX.
• Bits 23..0 – 3wb_, Data[23:0] 24-bit data word to be send on the 3-wire bus. MSB is sent first. Note: Default Value: 00000000 hex IntStatus addr: 600054 hex R 32 bits • Bits 31..13 – Reserved • Bit 12 – TxFifoAlmEmpty_IntStatus TX FIFO almost empty interrupt status. • Bit 11 – RxFifoAlmFull_IntStatus RX FIFO almost full interrupt. • Bit 10 – GenPurpTim_ IntStatus General purpose compare timer interrupt. • Bit 9 – TxAcCodeComplete_IntStatus RX/TX start compare timer interrupt enable.
AT76C551 • Bit 11 – RxFifoAlmFull_ IntEnable RX FIFO almost full interrupt enable. • Bit 10 – GenPurpTim_IntEnable General purpose compare timer interrupt enable. • Bit 9 – TxAcCodeComplete_IntEnable TX of Access Code has been completed. • Bit 8 – RxTxStart_ IntEnable RX/TX start compare timer interrupt enable. • Bit 7 – TxPktComplete_IntEnable TX packet completion interrupt enable. • Bit 6 – RxCorrelTrig_IntEnable Correlator trigger interrupt enable. • Bit 5 – RxHecFail_IntEnable HEC fail interrupt enable.
Clears HEC fail interrupt • Bit 4 – RxCrcFail_IntClear Clears CRC fail interrupt • Bit 3 – RxFecFail_IntClear Clears FEC fail interrupt • Bit 2 – RxPktHeaderRdy_IntClear Clears RX packet header arrival interrupt • Bit 1 – RxPayHeaderRdy_IntClear Clears RX payload header arrival interrupt • Bit 0 – RxPayloadRdy_IntClear Clears RX payload completion interrupt All events related to packet RX/TX as well as events generated by compare timers can activate the “Bluetooth Baseband” system interrupt.
AT76C551 • Bits 31..8 – Reserved • Bits 7..0 – RX_byte[7:0] Least recent received byte not yet read Note: Please note that reading RxFifoReadPort register is meaningful only if RX FIFO level is at least one, i.e. at least one byte exists in RX FIFO. If RX FIFO is not serviced before it is full it will overflow and subsequent bytes received will be lost. RX FIFO capacity is 64 bytes. TxFifoCtrlStatus addr: 600068 hex R/W 32 bits • Bits 31..
1: 23 Frequency Hop System • Bit0 – HopSelEnable_Busy Set by firmware and enables hardware frequency pointer calculation. Cleared by hardware when calculation is finished Note: Default Value: 00000000 hex hopSel_ABCDE addr: 600074 hex RW 32 bits • Bits 31..30 – Reserved • Bits 29..25 – A[4:0] Hop kernel register A • Bits 24..21 – B[4:0] Hop kernel register B • Bits 20..16 – C[4:0] Hop kernel register C • Bits 25..7 – D[4:0] Hop kernel register D • Bits 6..
AT76C551 Kc0 addr: 600080 hex W 32 bits • Bits 31..0 – Kc0[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc1 addr: 600084 hex W 32 bits • Bits 31..0 – Kc1[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc2 addr: 600088 hex W 32 bits • Bits 31..0 – Kc2[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc3 addr: 60008C hex W 32 bits • Bits 31..
ArReg2 addr: 600098 hex RW 32 bits • Bits 31..0 – ArReg2[31:0] Used in E_functions. Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex ArReg3 addr: 60009C hex RW 32 bits • Bits 31..0 – ArReg3[31:0] Used in E_functions. Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex KeyReg0 addr: 60000 hex RW 32 bits • Bits 31..
AT76C551 Voice CODEC Register Set The Voice CODEC has four modes: CVSD, A-law, U-law and pass through where data is transferred out through the digital interface. The module has independent receive and transmit paths – each having a dedicated 32-byte FIFO. VC_CTRL: Voice CODEC Analog Control addr: 500000 hex R/W 13 bits • Bits 15..13 – Reserved • Bit 12 – Rate 1= 64 kHz sampling rate 0= 8 kHz sampling rate • Bits 11..
• Bit 3 – DIR: Audio Clock Direction 1= Digital interface is slave 0= Digital interface is master • Bit 2 – BDIV: Divides Audio Clock Divides Audio Clock (depending on mode[4] bit) in order to drive the bit clock. {mode[2], mode[4]} = 00, abclk = aclk/32 {mode[2], mode[4]} = 01, abclk = aclk/16 {mode[2], mode[4]} = 10, abclk = aclk/24 {mode[2], mode[4]} = 11, abclk = aclk/12 • Bits 1..
AT76C551 VC_RxReadPort: Voice CODEC Receive FIFO Read Port addr: 500010 hex R 8 bits • Bits 7..0 – VC_RXD[7:0]: Receive Data Note: Default Value: 00 hex VC_TxFifoCtrl: Voice CODEC Transmit FIFO Control Status Register addr: 500014 hex R/W 16 bits • Bit 15 – EMPTY • Bit 14 – ALEMPTY 1 byte left to be transmitted. • Bit 13 – FULL • Bit 12 – RESFF: Reset Transmit FIFO • Bits 11..10 – Reserved • Bits 9..5 – TXFTR[4:0]: Transmit FIFO threshold • Bits 4..
USB Registers – USB Wrapper Registers The following registers are found in the USB wrapper block and control the overall performance of the USB hardware block. They provide status information, allow interrupt masking and DMA programming for fast data transfers between the DPRAM and the endpoint buffers.l Table 4.
AT76C551 Table 4.
SLP_MD_EN: Sleep Mode Control addr 5000000h R/W 8 bits • Bits 7..6 – Reserved • Bit 5 – SLP Put the USB module in sleep mode • Bits 4..0 – Reserved Note: Default: 00h GLB_IRQ_MSK: Global Interrupt Master Register addr 5000004h R/W 16 bits • Bits 15..
AT76C551 • Bit 6 – INTER_LINE The INTERRUPT line from the USB protocol handler is asserted. • Bits 5..2 – Reserved • Bit 1 – SUSP When this bit is high, the USB has entered the suspend state. • Bit 0 – RSM When this bit is high, the USB has entered the resume state. Note: Default: 00h RES_STAT: Reset Status addr 500000Ch R/W 8 bits • Bits 7..5 – Reserved • Bit 4 – USB_RES Set when USB module enters reset state. • Bits 3..
USB_DMA_FADD: DMA Target Endpoint Address addr 5000020h R/W 16 bits • Bits 7..0 – FAD[7:0]: USB Target Endpoint FIFO Address Note: Default: 00h This register is programmed with the address of the Endpoint FIFO Register of the USB block that the DMA operation is going to transfer bytes from/to. The addresses of the six endpoints supported by the USB block are listed in Table 5. Table 5.
AT76C551 • Bits 15..9 – Reserved • Bits 8..0 – UTDL[8:0]: USB Transmit DMA Length Note: Default: 00h The ARM programs this register with the number of bytes to be transferred during the next DMA. USB_TDMA_LENR: Transmit DMA Packet Length Transferred addr 5000048h R 8 bits • Bits 7..0 UTDL[7:0]: Transmit DMA Transferred Length Note: Default: 00h After the end of a DMA, the contents of this register reflect the number of bytes that have been transferred from main system memory to the transmit FIFO.
• Bit 2 R – RMWUPE Remote Wake-up Enable. This bit is set if the Host enables the function’s remote wake-up feature. • Bit 1 R – CONFG Configured. This bit is set by the firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0. • Bit 0 R – FADD Enable: Function Address Enable This bit is set by firmware after the status phase of a SET_ADRESS request transaction. The Host will use the new address starting at the next transaction.
AT76C551 • Bit 7 – Reserved • Bit 6 – EP6 INT: Endpoint 6 Interrupt • Bit 5 – EP5 INT: Endpoint 5 Interrupt • Bit 4 – EP4 INT: Endpoint 4 Interrupt • Bit 3 – EP3 INT: Endpoint 3 Interrupt • Bit 2 – EP2 INT: Endpoint 2 Interrupt • Bit 1 – EP1 INT: Endpoint 1 Interrupt • Bit 0 – EP0 INT: Endpoint 0 Interrupt Note: Default: 00h The function interrupt bits will be set by the hardware whenever the following bits in the corresponding Endpoint’s Control and Status Register are modified by the USB hardware: 1.
0 = Disable interrupt FADDR: Function Address Register addr 50003C8h R 8 bits • Bit 7 – FEN: Function Enable • Bits 6..0 – FADD[6:0]: Function Address Note: Default: 00h The FIU address register contains the function address assigned by the Host. This Function Address Register must be programmed by the processor once it has: 1. Received a SET_ADDRESS command from the Host. 2. Completed the status phase of the transaction. After power up or reset this register will contain the value of 0x00.
AT76C551 Table 6. Endpoint Type Note: Bit 1 Bit 0 Type 0 0 Control 0 1 Isochronous 1 0 Bulk 1 1 Interrupt Default: 00h Table 7.
Table 8. Endpoint Control and Status Register addr: see below 8 bits Bit Bit Name Function Description of Bit Bit 7 R Control Direction Set by the processor to indicate to the USB hardware the direction of a control transfer. 0 = control write. No data stage 1 = control read This bit is used by Control Endpoints only. This bit is only used by Control Endpoints. It is used by firmware to indicate the direction of a control transfer.
AT76C551 Table 8. Endpoint Control and Status Register (Continued) addr: see below 8 bits Bit Bit Name Function Description of Bit Bit 2 W RX Setup The USB hardware sets this bit when it receives a valid setup packet from the Host. This bit is used by Control Endpoints only. This bit is used only by Control Endpoints to signal the processor that the USB hardware has received a valid SETUP packet, and that the data portion of the packet is stored in the FIFO.
UART Register Set In Table 10, the register file and its fields are briefly presented. A more detailed description is provided in the following sections. Table 10. UART Register File and Register Fields Addr.
AT76C551 US_RHR: Receive Holding Register addr: 700000 hex R 8 bits • Bits 7..0 – US_RHR[7:0] Received data Note: Default Value: 00 hex US_THR: Transmit Holding Register addr: 700000 hex W 8 bits • Bits 7..0 – US_THR[7:0] Transmit data Note: Default Value: 00 hex US_IER: Interrupt Enable Register addr: 700004 hex R/W 8 bits • Bit 7 – TXEI: Transmitter Empty Interrupt When set the interrupt is enabled.
US_FCR: FIFO Control Register addr: 700008 hex R/W 8 bits • Bits 7..6 RCVR[1:0]a; RCVR Trigger Bits These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. • Bits 5..4 – Reserved • Bit 3 – RDMA: DMA Mode Select. When set the DMA is in burst mode according to the value in US_FCR. When it is cleared the characters are read one byte each time. • Bit 2 – Reserved • Bit 1 – FRS: FIFO Reset When set, resets the receive FIFO.
AT76C551 10: No parity 11: Multi drop • Bit 1 – RES: Parity Type In normal parity mode this bit is used for the determination of parity. In force parity mode this bit is forced to be the parity bit. • Bit 0 – LSB: Reserved Note: Default Value: 00 hex US_MR: Mode Register addr: 700010 hex R/W 8 bits • Bits 7..6 – CHM[1:0] Channel Mode 00: Normal 01: Automatic echo 10: Local loop-back 11: Remote loop-back • Bits 5..
• Bit 0 – RHR: Receive Holding Register Ready When set indicates that the Receive Holding Register is full. In order to clear this bit you must empty the RHR (or the FIFO if it is enabled) by reading the US_RHR register. Note: Default Value: 00 hex US_CR: Control Register addr: 700018 hex R/W 8 bits • Bit 7 – RXEN: Enable When set, this enables the receiver block of UART. • Bit 6 – RLES: Reset Line Error Status bits When set, this resets the PE, FE, OE bits of US_CSR register.
AT76C551 Table 12. Baud Rate Generation Example (Internal UART Clock = 14,76923 MHz) Baud Rate US_BM (hex) US_BL (hex) Error % 100 24 00 0.16 200 12 00 0.16 400 09 00 0.16 600 06 00 0.16 1200 03 00 0.16 2400 01 80 0.16 4800 00 C0 0.16 9600 00 60 0.16 19200 00 30 0.16 28800 00 20 0.16 38400 00 18 0.16 57.6K 00 10 0.16 115.2K 00 08 0.16 230.4K 00 04 0.16 307.2K 00 03 0.16 460.8K 00 02 0.16 921.6K 00 01 0.
• Bit 5 – CD: Carrier Detect Active high. This bit is the compliment of the CD input pin. • Bit 4 – CTS: Clear To Send Active high. This bit is the compliment of the CTS input pin. • Bit 3 – DSR Change Active high Logic 0: No DSR change Logic 1: The DSR input pin has changed state since the last time it was read. An interrupt will be generated. • Bit 2 – RI: Ring Indicator Change Active high Logic 0: No RI change Logic 1: The RI input pin has changed state since the last time it was read.
AT76C551 US_MCC: Modem Control Register addr: 700030 hex R/W 8 bits • Bit 7 – Reserved • Bit 6 – LB RI Value The compliment of the value of RI input, when Modem Control Loop Back mode is enabled. • Bit 5 – LB CD Value The compliment of the value of CD input, when Modem Control Loop Back mode is enabled. • Bit 4 – MC LB EN: Modem Control Loop Back Mode Enable • Bit 3 – DSR Change Mask This bit when set enables the DSR change interrupt.
General Purpose Registers Power Down addr: D00000 hex R/W 6 bits • Bit 5 – VCPU: VC Power Up • Bit 4 – UARTPU: UART Power Up • Bit 3 – USBPU: USB Power Up • Bit 2 – BDPRPD: BT Baseband Power Down • Bit 1 – Reserved • Bit 0 – ARMSPD: ARM Speed Note: Default Value: 00 hex Module Reset addr: D00004 hex R/W 5 bits • Bit 4 – PCMCIARES: PCMCIA Core Reset • Bit 3 – USBRES: USB Reset • Bit 2 – VCRES: VC Reset • Bit 1 – UARTRES: UART Reset • Bit 0 – BTRES: BT Baseband Reset Note: Default Value: 00 hex USB
AT76C551 Interrupt Mask Register addr: F00004 hex R/W 8 bits • Bit 7 – VC Mask Enables the Voice Codec interrupt • Bit 6 – PCMCIA Mask Enables the PCMCIA interrupt • Bit 5 – UART Mask Enables the UART interrupt • Bit 4 – USB Mask Enables the USB interrupt • Bit 3 – BDPR Mask Enables the Baseband DPRAM interrupt • Bit 2 – BT Mask Enables the Baseband and Timers interrupt • Bit 1 – TM1 Mask Enables the Timer 1 Interrupt • Bit 0 – TM2 Mask Enables the Timer 2 Interrupt Note: Default Value: 00 hex Interrup
• Bit 1 – TM1_PR Enables FIQ priority for the Timer 1 interrupt line • Bit 0 – TM2_PR Enables FIQ priority for the Timer 2 interrupt line Note: Timer Device Registers Default Value: 00 hex AT76C551 incorporates two identical and completely independent system timer devices, Timer Device 1 and Timer Device 2. Each Timer Device is implemented as a 32-bit down counter which advances at a programmable rate driven by a prescale circuit.
AT76C551 Timer Prescale Register R/W 16 bits Timer Prescale Register sets the divisor for the prescale circuit. If Timer Prescale Register contains p and PAI clock frequency is f (MHz) then countdown rate for the Timer Device counter will be r = f/p Note: The Timer Prescale Register must contain a non-zero value for proper Timer Device operation. Timer Control Register R/W 16 bits • Bits 15..2 – Reserved Returns 0 when read • Bit 1 – Enable Logic 1: The counter is allowed to run.
Electrical Specifications Recommended Operating Conditions Table 14 shows the range for which Atmel library cells have been characterized. Operation of a device outside this range may result in the device failing to meet some of its specification. Table 14. Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VDD3 DC Supply Voltage Core and Standard I/Os 3.0 3.3 3.
AT76C551 DC Characteristics The values shown in this table are valid for TA = 0°C to 85°C, VCC = 3.3V unless otherwise noted. Oscillator Signals: XIN, XOUT Table 16. Power Supply Symbol Parameter VCC Condition Min Max Unit Power Supply 3.3 V ICC Supply Current 50 mA ICCS Suspended Device Current 200 µA Table 17. USB Signals: DP, DM Symbol Parameter Condition Min Max Unit ILO High-Z Data Line Leakage 0V < Vin < 3.3V -10 +10 µA VDI Differential Input Sensitivity DPx and DMx 0.
AC Characteristics Table 19. DP, DM Driver Characteristics Symbol Parameter Condition Min Max Unit tR Rise Time CL = 50 pF 4 20 ns tF Fall Time CL = 50 pF 4 20 ns tRFM TR/TF Matching 90 110 % VCRS ZDRV (1) Note: Output Signal Crossover Except First Transition From Idle State 1.3 2.0 V Driver Output Resistance Steady State Drive 29 44 W 1. With external 27W series resistor Table 20.
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