Owner manual

23
AT76C551
1612D–08/01
Register
Description
Memory Controller
Register Set
The Memory Controller Register Set can be configured to cooperate with various types of
external Flash and SRAM memories. The configuration parameters are held by Memory Con-
figuration Registers (MCR) which are mapped into AMBA
™
memory space. After AT76C551
resets, MCR default values guarantee correct operation of external Flash or SRAM memories
connected to AT76C551. AT76C551 firmware adjusts MCR in order to achieve Flash and
SRAM safe operation with minimum wait states.
In the reset configuration the external Flash can be found at the bottom of the address map. If
the bit 0 of the remap register is set high, then the Memory Controller switches to the normal
memory map in where there is internal SRAM.
SRAM Configuration Register (MCR0)
addr: E00000 hex R/W 8 bits
• Bit 7 – Reserved
• Bits 6..4 – SWW[2:0]
Number (0 - 7) of wait states during SRAM write cycles
• Bit 3 – Reserved
• Bits 2..0 – SWR[2:0]
Number (0 - 7) of wait states during SRAM read cycles
Note: Default Value: 77 hex
Flash Memory Configuration Register (MCR1)
addr: E00004 hex R/W 8 bits
• Bits 7 – Reserved
• Bits 6..3
Number (0 - 7) of wait states during write access of Flash memory latches
• Bits 2..0 – FWR[2:0]
Number (0 - 7) of wait states during Flash memory read cycles
Note: Default Value: 07 hex
Flash and Internal SRAM remap Register (MCR2)
addr: E00008 hex R/W 8 bits
• Bits 7..1 – Reserved
• Bit 0 – REMAP
Remap enable
Note: Default Value: 00 hex