Owner manual

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AT76C551
1612D–08/01
• Bit 6 – CORES: Core Reset
While this bit is set, AT76C551 units on the AMBA bus (including ARM core) are held in reset
state. When this bit is cleared, AT76C551 units on the AMBA bus exit reset state and ARM
core, in particular, begins code execution by fetching its reset exception vector.
Note: This bit is not automatically cleared after it is set.
• Bit 5 – 16/8-bit: 16/8-bit Access Mode
If set, enables the 16-bit access of PCMCIA module with the system memory. If cleared, the
access is 8-bit (see SIR1 - SIR5).
• Bit 4 – Reserved
• Bit 3 – AIH: ARM Interrupt to Host
This bit is set if an interrupt to the host has been generated by the ARM core (see bit AIH of
MIR0) and is still pending. To acknowledge the interrupt and clear this bit, the host driver soft-
ware must write 1 on this bit.
• Bit 2 – HIA: HOst Interrupt to ARM
When this bit is set by the host, an interrupt to the ARM core is generated (see bit HIA of
MIR0). This bit is automatically cleared when the ARM core acknowledges the interrupt (see
MIR0).
• Bit 1 – AIHEN: ARM to Host Interrupt Enable
Logic 0: Interrupts from ARM core to the host disabled
Logic 1: Interrupts from ARM core to the host enabled
• Bit 0 – Reserved
Note: Default Value: 00 hex – The host driver software is responsible for AT76C551 reset. The host
driver software has to set CORES bit of GCR first. This will reset ARM core and all other units
on AMBA bus. The host driver must next set SWRES bit of GCR. This will reset SIR and clear
both CORES and SWRES bits, forcing ARM core to leave reset state and begin firmware pro-
gram execution.
SIR1 – AMBA BSR: Bank Select Register
PCMCIA addr: 0001 hex R/W 8 bits
• Bits 7..4 – AD[23:20]
This register is used by the host in conjunction with SIR2, SIR3, SIR4 and SIR5 in order to
access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA
interface unit. Each time DLR (SIR4) is accessed, the AMBA Bank Select Register (BSR)
drives AMBA address lines 23…20 and 18…15. AMBA address line 19 is always driven to
logic 0.
• Bits 3..0 – AD[18:15]
Note: Default Value: 00 he
SIR2 – AMBA ALSR: Address Low Select Register
PCMCIA addr: 0002 hex R/W 8 bits
• Bits 7..0 – AD[7:0]
This register is used by the host in conjunction with SIR1, SIR3, SIR4 and SIR5 in order to
access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA
interface unit. Each time SIR4 is accessed, the AMBA ALSR drives AMBA address lines 7..0.
Note: Default Value: 00 hex