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5390A–BDC–06/04

Features

• Dual ADC with 8-bit Resolution

• 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode

• Single or 1:2 Demultiplexed Output

• LVDS Output Format (100Ω)

• 500 mVpp Analog Input (Differential Only)

• Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

• Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)

• LQFP144 Package

• Temperature Range:

– 0°C < T

< 70°C (Commercial Grade)

– -40°C < T

< 85°C (Industrial Grade)

• 3-wire Serial Interface

– 16-bit Data, 3-bit Address

– 1:2 or 1:1 Output Demultiplexer Ratio Selection

– Full or Partial Standby Mode

– Analog Gain (±1.5 dB) Digital Control

– Input Clock Selection

– Analog Input Switch Selection

– Binary or Gray Logical Outputs

– Synchronous Data Ready Reset

– Data Ready Delay Adjustable on Both Channels

– Interlacing Functions:

Offset and Gain (Channel to Channel) Calibration

Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel

– Internal Static or Dynamic Built-In Test (BIT)

Performance

• Low Power Consumption: 0.7W per Channel

• Power Consumption in Standby Mode: 120 mW

• 1 GHz Full Power Input Bandwidth (-3 dB)

• SNR = 43 dB Typ (7.0 ENOB), THD = -53 dBc, SFDR = -55 dBc at Fs = 500 Msps

Fin = 250 MHz

• 2-tone IMD3: -54 dBc (249 MHz, 251 MHz) at 500 Msps

• DNL = 0.25 LSB, INL = 0.5 LSB

• Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)

• Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)

• Low Bit Error Rate (10

-15

) at 500 Msps

Application

• Instrumentation

• Satellite Receivers

• Direct RF Down Conversion

• WLAN

Dual 8-bit

500 Msps ADC

AT84AD004

Smart ADC

Summary of content (58 pages)

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Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format (100Ω) 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs Power Supply: 3.3V (Analog), 3.3V (Digital), 2.
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Description The AT84AD004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 500 Msps and an input frequency bandwidth of 1 GHz.
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AT84AD004 Figure 1.
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Typical Applications Figure 2. Satellite Receiver Application Satellite Low Noise Converter (Connected to the Dish) Bandpass Amplifier Low Pass Filter Bandpass Amplifier 11..12 GHz Dish Satellite Tuner Tunable Band Filter IF Band Filter AGC 1..2 GHz Synthesizer 1.5 … 2.5 GHz Local Oscillator I I I Local Oscillator Control Functions: AT84AD004 Clock and Carrier 90 Q Recovery...
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AT84AD004 Figure 3. Dual Channel Digital Oscilloscope Application DAC Gain A Channel A A Analog Switch Channel B ADC B DAC Offset FISO RAM DAC Offset Display µP ADC A DAC Gain Channel Mode Selection Clock Selection Timing Circuit DACs Smart Dual ADC DACs Absolute Maximum Ratings Parameter Symbol Value Unit Analog positive supply voltage VCCA 3.6 V Digital positive supply voltage VCCD 3.6 V Output supply voltage VCCO 3.6 V VCCA to VCCD ± 0.8 V VCCO 1.
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Recommended Conditions of Use Parameter Symbol Comments Recommended Value Unit Analog supply voltage VCCA 3.3 V Digital supply voltage VCCD 3.3 V Output supply voltage VCCO 2.
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AT84AD004 Table 1. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Typ Max ICCA ICCD ICCO 150 290 180 180 350 215 ICCA ICCD ICCO 80 160 55 95 190 65 mA mA mA Supply current (1 channel only, 1:2 DMUX mode) - Analog - Digital - Output ICCA ICCD ICCO 80 170 90 95 205 110 mA mA mA Supply current (full standby mode) - Analog - Digital - Output ICCA ICCD ICCO 12 24 3 17 34 5 mA mA mA Nominal dissipation (1 clock, 1:1 DMUX mode, 2 channels) PD 1.4 1.
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Table 1. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Symbol Min Typ Max Unit Output levels (assuming VCCO = 2.25V) 100Ω differentially terminated Logic 0 voltage Logic 1 voltage VOL VOH 1.0 1.25 1.1 1.35 1.2 1.45 V V Output offset voltage (assuming VCCO = 2.
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AT84AD004 Table 3. AC Performances Parameter Symbol Min Typ Max Unit 42 44 dBc 41 43 dBc 42 dBc 7 7.2 Bits 6.7 7.0 Bits 6.
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Table 4. AC Performances in Interlace Mode Parameter Symbol Min Typ Max Unit Maximum equivalent clock frequency Fint = 2 x Fs Where Fs = external clock frequency Fint 1 Minimum clock frequency Fint 20 Msps Differential non-linearity in interlace mode intDNL 0.25 LSB Integral non-linearity in interlace mode intINL 0.5 LSB 42 dBc 40 dBc 7.1 Bits 6.
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AT84AD004 Table 5. Switching Performances Parameter Symbol Min Typ Max Unit Switching Performance and Characteristics - See “Timing Diagrams” on page 12. Maximum operating clock frequency FS 500 Minimum clock frequency (no transparent mode) Minimum clock frequency (with transparent mode) FS Msps 10 Msps 1 Ksps Minimum clock pulse width [high] (No transparent mode) TC1 0.4 1 50 ns Minimum clock pulse width [low] (No transparent mode) TC2 0.
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Timing Diagrams Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q Address: D7 D6 D5 D4 D3 D2 D1 D0 1 1 X X 1 X 0 0 TA N+3 N+1 VIN N+2 N CLKI or CLKQ Pipeline delay = 4 clock cycles DOIA[0:7] or DOQA[0:7] N-4 TDO Pipeline delay = 3 clock cycles DOIB[0:7] or DOQB[0:7] N N - 2 N-3 TDO N-1 N +1 Programmable delay TD2 CLKOI or CLKOQ (= CLKI/2) CLKOI or CLKOQ (= CLKI/4) Figure 5.
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AT84AD004 Figure 6.
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Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q Address: D7 D6 D5 D4 D3 D2 D1 D0 1 0 X X 0 X 0 0 TA N+3 N+1 VIN N+2 N CLKI TDO Pipeline delay = 3.
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AT84AD004 Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Address: D7 D6 D5 D4 D3 D2 D1 D0 0 X X X 1 X 0 0 N+6 N+4 N+2 TA N+5 VIN N N+1 N+3 CLKI CLKIN TDO Pipeline delay = 4 clock cycles DOQA[0:7] N -8 Pipeline delay = 3 clock cycles DOQB[0:7] N N- 4 N -6 TDO N -2 Pipeline delay = 3.
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Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Address: D7 D6 D5 D4 D3 D2 D1 D0 0 X X X 0 X 0 0 N+6 N+4 N+2 TA N+5 VIN N N+3 N+1 CLKI CLKIN TDO Pipeline delay = 3.5 clock cycles DOQA[0:7] N -6 N -4 N -5 N+2 N +1 N+3 TDO Pipeline delay = 3 clock cycles DOIA[0:7] N N - 2 N -3 N - 1 CLKOI (= CLKI/2) DOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impedance Figure 10.
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AT84AD004 Figure 11. Data Ready Reset 500 ps CLKI or CLKQ 500 ps 1 ns min DDRB FORBIDDEN FORBIDDEN ALLOWED ALLOWED Figure 12. Data Ready Reset 1:1 DMUX Mode TA N VIN N+1 Clock in Reset CLKI or CLKQ Pipeline Delay + TDO DOIA[0:7] or DOQA[0:7] N TDR CLKOI or CLKOQ TDR 2 ns DDRB 1 ns min Note: The Data Ready Reset is taken into account only 2 ns after it is asserted.
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Figure 13. Data Ready Reset 1:2 DMUX Mode TA N VIN N+1 Clock in Reset CLKI or CLKQ Pipeline Delay + TDO DOIA[0:7] or DOQA[0:7] N DOIB[0:7] or DOQB[0:7] N+1 TDR TDR CLKOI or CLKOQ (= CLKI/2) TDR + 2 cycles CLKOI or CLKOQ (= CLKI/4) TDR + 2 cycles 2 ns DDRB 1 ns min Notes: 1. In 1:2 DMUX, Fs/2 mode: The Data Ready Reset is taken into account only 2 ns after it is asserted.
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AT84AD004 Functions Description Table 6. Description of Functions Name Function VCCA Positive analog power supply VCCD Positive digital power supply VCCO Positive output power supply GNDA Analog ground GNDD Digital ground GNDO Output ground VINI, VINIB Differential analog inputs I VINQ, VINQB Differential analog inputs Q CLKOI, CLKOIN, CLKOQ, CLKOQN Differential output data ready I and Q VCCA = 3.3V VCCD = 3.3V VCCO = 2.
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Digital Output Coding (Nominal Settings) Table 7.
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AT84AD004 Table 8. AT84AD004 LQFP 144 Pin Description (Continued) Symbol Pin number Function CLKQN 128 Inverted phase (-) clock input signal (CLKQ) DDRB 126 Synchronous data ready reset I and Q DDRBN 127 Inverted phase (-) of input signal (DDRB) DOAI0, DOAI1, DOAI2, DOAI3, DOAI4, DOAI5, DOAI6, DOAI7 117, 113, 105, 101, 93, 89, 81, 77 In-phase (+) digital outputs first phase demultiplexer (channel I) DOAI0 is the LSB.
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Table 8. AT84AD004 LQFP 144 Pin Description (Continued) Symbol Pin number Function CLKOIN 122 Inverted phase (-) output clock channel I CLKOQ 132 Output clock in-phase (+) channel Q, 1/2 input clock frequency CLKOQN 131 Inverted phase (-) output clock channel Q VtestQ, VtestI 52, 53 Pins for internal test (to be left open) Cal 70 Calibration output bit status Vdiode 35 Positive node of diode used for die junction temperature measurements Figure 14.
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AT84AD004 Typical Characterization Results Nominal conditions (unless otherwise specified): Typical Full Power Input Bandwidth • VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.
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Typical Crosstalk Figure 16. Crosstalk (Fs = 500 Msps) 80 70 60 dBc 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 Fin (MHz) Note: Typical DC, INL and DNL Patterns Measured on the AT84AD004TD-EB Evaluation Board. 1:2 DMUX mode, Fs/4 DR type Figure 17.
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AT84AD004 Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input) 0.3 0.2 DNL (Lsb) 0.1 0 -0.1 -0.2 -0.3 1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256 Codes Typical Dynamic Performances Versus Sampling Frequency Figure 19. ENOB Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) 7.6 7.4 ENOB (Bit) 7.2 7.0 6.8 6.6 6.4 6.2 6.0 50 100 150 200 250 300 350 400 450 500 550 Fs (Msps) Figure 20.
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Figure 21. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) -48 -50 THD (dBc) -52 -54 -56 -58 -60 50 100 150 200 250 300 350 400 450 500 550 Fs (Msps) Figure 22. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) 45 SNR (dBc) 44 43 42 41 40 50 100 150 200 250 300 350 400 450 500 550 Fs (Msps Typical Dynamic Performances Versus Input Frequency Figure 23. ENOB Versus Input Frequency (Fs = 500 Msps) 7.6 7.4 ENOB (Bit) 7.2 7.0 6.8 6.6 6.4 6.
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AT84AD004 Figure 24. SFDR Versus Input Frequency (Fs = 500 Msps) -46 -48 -50 SFDR (dBc) -52 -54 -56 -58 -60 -62 -64 0 100 200 300 400 500 400 500 Fin (MHz) Channel I Channel Q Figure 25. THD Versus Input Frequency (Fs = 500 Msps) -48 -49 -50 THD (dBc) -51 -52 -53 -54 -55 -56 -57 -58 0 100 200 300 Fin (MHz) Channel I Channel Q Figure 26.
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Typical Signal Spectrum Figure 27. Fs = 500 Msps and Fin = 20 MHz (1:2 DMUX, Fs/4 DR Type FiSDA = -35 ps, ISA = -50 ps) 20 Fundamental: H1 0 -20 SFDR = -60 dBc dBc -40 H2 H3 -60 H4 -80 -100 -120 0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234 Fs (Msps) Figure 28.
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AT84AD004 Figure 29. Fs = 500 Msps and Fin = 500 MHz (1:2 DMUX, Fs/4 DR Type FiSDA = -35 ps, ISA = -50 ps) 20 Fundamental: H1 0 -20 SFDR = -57 dBc H2 -40 dBc H3 -60 -80 -100 -120 0 Note: 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234 Fs (Msps) The spectra are given with respect to the output clock frequency observed by the acquisition system (Figures 27 to 29). Figure 30.
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Typical Performance Sensitivity Versus Power Supplies and Temperature Figure 31. ENOB Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) 7.6 ENOB (Bit) 7.4 7.2 7.0 6.8 6.6 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 Vcca (V) Channel I Channel Q Figure 32. SFDR Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -48 -50 SFDR (dBc) -52 -54 -56 -58 -60 -62 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.
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AT84AD004 Figure 33. THD Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -48 -49 -50 THD (dBc) -51 -52 -53 -54 -55 -56 -57 -58 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 Vcca (V) Channel I Channel Q Figure 34. SNR Versus VCCA (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) 46.0 SNR (dBc) 45.0 44.0 43.0 42.0 41.0 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.
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Figure 35. ENOB Versus Junction Temperature (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) 7.4 7.2 500 Msps 20 MHz ENOB (Bit) 7.0 500 Msps 250 MHz 6.8 500 Msps 500 MHz 6.6 6.4 6.2 6.0 -50 -25 0 25 50 75 100 Tj (˚C) Figure 36.
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AT84AD004 Figure 37. THD Versus Junction Temperature (Fs = 500 Msps, Fin = 250 MHz, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -44 THD (dBc) -46 -48 500 Msps 500 MHz -50 500 Msps 250 MHz 500 Msps 20 MHz -52 -54 -56 -58 -50 -25 0 25 50 75 100 Tj (˚C) Figure 38.
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Test and Control Features 3-wire Serial Interface Control Setting Table 9. 3-wire Serial Interface Control Settings Mode Characteristics Mode = 1 (2.
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AT84AD004 3-wire Serial Interface and Data Description The 3-wire bus is activated with the control bit mode set to 1. The length of the word is 19 bits: 16 for the data and 3 for the address. The maximum clock frequency is 50 MHz. Table 10.
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Table 10.
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AT84AD004 Table 11.
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Table 11. 3-wire Serial Interface Data Setting Description (Continued) Setting for Address: 000 D15 D14 D13 D12 D11 D10 D9(1) D8 D7 D6 D5 D4 D3 D2 D1 D0 Control wait bit calibration(6) X X a b X X 0 X X X X X X X X X In 1:2 DMUX FDataReady I & Q = Fs/2 X 0 X X X X 0 X X X X X X X X X In 1:2 DMUX FDataReady I & Q = Fs/4 X 1 X X X X 0 X X X X X X X X X Notes: 1. 2. 3. 4.
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AT84AD004 • A minimum of one clock cycle with “sldn” returned at 1 is requested to close the write procedure and make the interface ready for a new write procedure. Any clock cycle where “sldn” is at 1 before the write procedure is completed interrupts this procedure and no further data transfer to the internal registers is performed.
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Table 12.
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AT84AD004 The calibration phase is necessary when using the AT84AD004 in interlace mode, where one analog input is sampled at both ADC cores on the common input clock’s rising and falling edges. This operation is equivalent to converting the analog signal at twice the clock frequency Table 13. Matching Between Channels Value Parameter Min Gain error (single channel I or Q) without calibration Gain error (single channel I or Q) with calibration -0.5 0 -0.5 0 Unit LSB 0.
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Example: Address = 110 Data = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 1 0 1 0 1 0 1 0 1 One should then obtain 01010101 on Port B and 10101010 on Port A. When the dynamic mode is chosen (Data1 = 1) port B outputs a rising ramp while Port A outputs a decreasing one. Note: Decimation Mode The decimation mode is provided to enable rapid testing of the ADC. In decimation mode, one data out of 16 is output, thus leading to a maximum output rate of 31.
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AT84AD004 The VBE diode’s forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure 43. Figure 43. Diode Characteristics Versus TJ 860 840 820 Diode Voltage (mV) 800 780 760 740 720 700 680 660 640 620 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Junction Temperature (˚C) VtestI, VtestQ VtestI and VtestQ pins are for internal test use only. These two signals must be left open. Equivalent Input/Output Schematics Figure 44.
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Figure 45. Simplified Data Ready Reset Buffer Model VCCD DDRB 100Ω 50Ω VCCD/2 50Ω 100Ω DDRBN GNDD Figure 46. Analog Input Model Vcca Vcca DC Coupling (Common Mode = Ground = 0V) 50Ω Vinl Reverse Termination Sel Input I ESD GND VinI VinI Double Pad GND – 0.
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AT84AD004 Figure 47. Data Output Buffer Model VCCO DOAIO, DOAI7 DOBIO, DOBI7 DOAION, DOAI7N DOBION, DOBI7N GNDO Definitions of Terms Table 14. Definitions of Terms Abbreviation Definition Description BER Bit Error Rate The probability of exceeding a specified error threshold for a sample at a maximum specified sampling rate.
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Table 14. Definitions of Terms (Continued) Abbreviation Definition Description ORT Overvoltage Recovery Time The time to recover a 0.
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AT84AD004 Table 14.
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Using the AT84AD004 Dual 8-bit 500 Msps ADC Decoupling, Bypassing and Grounding of Power Supplies The following figures show the recommended bypassing, decoupling and grounding schemes for the dual 8-bit 500 Msps ADC power supplies. Figure 48. VCCD and VCCA Bypassing and Grounding Scheme L PC Board 3.3V VCCD L 1µF VCCA 100 pF PC Board GND C C Figure 49. VCCO Bypassing and Grounding Scheme L VCCO PC Board 2.
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AT84AD004 Analog Input Implementation The analog inputs of the dual ADC have been designed with a double pad implementation as illustrated in Figure 51. The reverse pad for each input should be tied to ground via a 50Ω resistor. The analog inputs must be used in differential mode only. Figure 51.
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Figure 52. Termination Method for the ADC Analog Inputs in AC Coupling Mode 50Ω VinI 50Ω Source VinI Channel I GND VinIB GND 50Ω VinIB Dual ADC 50Ω VinQ 50Ω Source VinQ Channel Q GND VinQB GND 50Ω VinQB Clock Implementation The ADC features two different clocks (I or Q) that must be implemented as shown in Figure 53. Each path must be AC coupled with a 100 nF capacitor. Figure 53.
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AT84AD004 Figure 54. Single-ended Termination Method for Clock I or Clock Q VCCD AC coupling capacitor 50Ω Source R1 CLK 50Ω 50Ω AC coupling capacitor R2 CLKB 50Ω VCCD/2 Output Termination in 1:1 Ratio When using the integrated DMUX in 1:1 ratio, the valid port is port A. Port B remains unused. Port A functions in LVDS mode and the corresponding outputs (DOAI or DOAQ) have to be 100Ω differentially terminated as shown in Figure 55 on page 52.
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Figure 55.
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AT84AD004 Figure 56. Dual ADC and ASIC/FPGA Load Block Diagram Data rate = FsI/2 Port A DEMUX 8 :16 Channel I Data rate = FsQ/2 Data rate = FsQ/4 CLKI/CLKIN @ FsI Dual 8-bit 1 Gsps ADC Port A Channel Q DMUX 8 :16 ASIC / FPGA Port B Channel I DMUX 8 :16 CLKQ/CLKQN @ FsQ Port B DMUX 8 :16 Channel Q Note: The demultiplexers may be internal to the ASIC/FPGA system.
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Thermal Characteristics Simplified Thermal Model for LQFP 144 20 x 20 x 1.4 mm The following model has been extracted from the ANSYS FEM simulations. Assumptions: no air, no convection and no board. Figure 57. Simplified Thermal Model for LQFP Package Silicon Junction 355 µm silicon die 25 mm 2 λ = 0.95W/cm/˚C 0.6˚C/watt 40 µm Epoxy/Ag glue λ = 0.02 W/cm/˚C 1.4˚C/watt Copper paddle λ = 2.5W/cm/˚C Package top Resin λ = 0.007W/cm/˚C 0.1˚C/watt 6.1˚C/watt 1.5˚C/watt 5.
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AT84AD004 Thermal Resistance from Junction to Ambient The thermal resistance from the junction to ambient is 25.2° C/W typical. Note: In order to keep the ambient temperature of the die within the specified limits of the device grade (that is TA max = 70°C in commercial grade and 85°C in industrial grade) and the die junction temperature below the maximum allowed junction temperature of 105°C, it is necessary to operate the dual ADC in air flow conditions (1m/s recommended).
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Ordering Information Part Number Package Temperature Range Screening Comments AT84XAD004TD LQFP 144 Ambient Prototype Prototype version Please contact your local Atmel sales office AT84AD004CTD LQFP 144 C grade 0°C < TA < 70°C Standard AT84AD004VTD LQFP 144 V grade -40°C < TA < 85°C Standard AT84AD004TD-EB LQFP 144 Ambient Prototype 56 Evaluation kit AT84AD004 5390A–BDC–06/04
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AT84AD004 Packaging Information Figure 58. Package Type N Dims. A A1 A2 D D1 E E1 L e b ddd ccc o 1 B E1 A E Notes: D D1 Body +2.00 mm footprint Tols. Leads 144L max. 1.60 0.05 min./0.15 max. +/- 0.05 1.40 +/-0.20 22.00 +/-0.10 20.00 +/-0.20 22.00 +/-0.10 20.00 +0.15/-0.10 0.60 basic 0.50 +/-0.05 0.22 0.08 max. 0.08 o 0 o- 5 1. All dimensions are in millimeters 2. Dimensions shown are nominal with tolerances as indicated 3. L/F: eftec 64T copper or equivalent 4.
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.