Features • • • • • • • • Multiband Transceiver: 400 MHz to 950 MHz Monochip RF Solution: Transmitter-Receiver-Synthesizer Integrated PLL and VCO: No External Coil Very Resistant to Interferers by Design Digital Channel Selection 200 Hz Steps Data Rates up to 64 kbps with Data Clock and no Manchester Encoding Required High Output Power Allowing Very Low Cost Printed Antennas: – +10 dBm in the 915 MHz Frequency Band – +12 dBm in the 868 MHz Frequency Band – +14 dBm in the 433 MHz Frequency Band • FSK Modulat
General Overview General Overview of Functioning The AT86RF211 is a microcontroller RF peripheral: all the user has to do is to write/read registers to setup the chip (i.e. frequency selection) or have information about parameters such as RSSI level, Vbattery, PLL lock state. All these operations are carried out via a three-wire serial interface. Normal Mode The chip is set-up by the microcontroller: frequency and mode (Rx or Tx).
AT86RF211 Figure 1. Reception and Transmit Mode F = Frequency of transmitted signal AT86RF211 (TRX01) SLE, SCK, SDATA (for set-up) Transmit mode 3 Companion Microcontroller DATAMSG AT86RF211 acts like a "pipe" (data is transmitted with NO processing): automatic data to frequency conversion.
Figure 2.
AT86RF211 Block Diagram Figure 4. AT86RF211 Block Diagram Optional RF FILTER AERIAL MATCHING CIRCUIT IF2 FILTER 455 kHz IF1 FILTER These are the only blocks that depend on the selected ISM band (433, 868 or 915 MHz): dual band applications can be done by only switching them. Synthesizer, loop filter, IF filter(s), power supply decoupling are identical. 10.7 MHz or 21.
Pin Description Table 1. Pinout Pin Name Comments Pin Name Comments 1 RPOWER Full scale output power resistor 25 SKFILT Threshold for data slicer 2 TXGND1 GND 26 DSIN Data slicer input 3 RF RF input/output 27 DISCOUT Discriminator output 4 TXGND2 GND 28 IF2VCC VCC 5 TXGND3 GND 29 IF2GND GND 6 TXGND4 GND 30 IF2IN IF2 amplifier input 7 TXVCC VCC 31 IF2DEC 2.
AT86RF211 Detailed Description Frequency Synthesis Crystal Reference Oscillator The reference clock is based on a classical Colpitts architecture with three external capacitors. An XTAL with load capacitor in the range of 10 pF - 20 pF is recommended. The bias circuitry of the oscillator is optimized to produce a low drive level for the XTAL. This reduces XTAL aging. Any standard, parallel mode 10.245 MHz or 20.945 MHz crystal can be used. Note: The PLL is activated only when the oscillator is stabilized.
Figure 7. Synthesizer Loop Filter Schematic VCO PFD & CHP Fref FILT1 Note: 8 VCOIN The PLL loop filter can be designed to optimize the phase noise around the carrier. Three configurations can be suggested, regarding the application and channel spacing: - Narrow band: (14.7 kΩ + 2.2 nF) // 220 pF - Typical: (3.3 kΩ + 5.
AT86RF211 Receiver Description Figure 8. Typical Expected Currents in Rx Mode Supply Current - Rx Mode 32.00 Isupply (mA) 868 or 915 MHz 30.00 433 MHz 28.00 26.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 Vsupply (V) Detailed Current - Rx Mode EVCC2 Supply Currents (mA) 10.00 8.00 6.00 EVCC1 RXVCC 4.00 CVCC2 CVCC1 AVCC 2.00 0.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 DIVCC IF2VCC TXVCC 4.
Overview and Choice of Intermediate Frequencies For selectivity and flexibility purpose, a classical and robust 2 IF superheterodyne architecture has been selected for the AT86RF211. In order to minimize the external components cost, the most popular IF values have been chosen. The impedances of the input/output of the mixing stages have been internally matched to the most usual ceramic filter impedances. Two typical IF values are suggested: • 10.7 MHz is the most popular option. • 21.
AT86RF211 Figure 10. TEM Filter 1 pF 1 pF λ /4 Zc = 7Ω TEM l = 0.75 (19 mm) Such a filter also provides an out-of-band interference rejection greater than 20dB, 40 MHz away from 433 MHz. First LNA/Mixer The main characteristics of the LNA/Mixer are typically: • Voltage gain: 17 dB for the LNA/Mixer; 11 dB if gain min. is selected • Bandwidth: 1.
Figure 11. Schematic Input of the LNA RXIN Figure 12. Schematic Output of the Mixer IF1OUT The first mixer translates the input RF signal down to 10.7 MHz or 21.4 MHz as chosen by the user. The local oscillator is provided by the same synthesizer which will generate a local frequency 10.7 MHz or 21.4 MHz away from the Tx carrier frequency. The output impedance of the mixer is 330Ω with a 20% accuracy, so that low cost, standard 10.7 MHz ceramic filters can be directly driven.
AT86RF211 Figure 13. IF1 Filtering IF1 Filter IF1OUT (pin 36) IF1IN (pin 35) "or" 330 Ω 330 Ω C > 100 pF Figure 14. Schematic Input of IF1 Amplifier IF1IN 330Ω 20 k Ω IF1DEC Figure 15. Schematic Output of the Second Mixer 1600 Ω IF2 Filtering and Gain IF2OUT IF2 filtering achieves a narrow channel selection. In case it is not used, it should be replaced by a > 1 nF coupling capacitor, thus the IF1 filter is the only part achieving the channel selection.
Figure 16. LC Band-pass Filter 10 nF 10 nF F1 F2 Filter gain global response Frequency ~ F1 ~ F2 40 kHz or higher IF2 Amplifier Chain • 10 nF capacitors cut DC response forward and backward. • The first network has the low cut-off frequency. • The second network has the high cut-off frequency. The input impedance of the IF2 amplifier is 1700Ω. This value enables the use of popular filters with impedance between 1500Ω and 2000Ω. It is directly connected to the FSK demodulator.
AT86RF211 RSSI Output The RSSI value can be read as a 6 bits word in the STATUS register. Its value is linear in dB as plotted below: Figure 18.
Figure 19. ADC Converter Input Selection STATUS register MRSSI RSSI Vcc supply M U X DISCOUT (MOFFSET) M U Voltage X M U X ADC MVCC CTRL1[1] CTRL1[24] Note: For voltage measurement, the LSB weighs 85 mV and the reference voltage is 1.25V. The ADC measuring the RSSI can be turned into voltage or discriminator output DC level measurement. FSK Demodulator Its structure is based on an oscillator: Figure 20.
AT86RF211 The input RBW resistor controls the discriminator bandwidth. This bandwidth is selected by CTRL1[6]. The default value is "standard discriminator BW". The slope of the discriminator increases by 5 mV/kHz/V with VCC and is 14 mV at 2.4V. Example: VCC = 3V implies +17 mV/kHz sensitivity for the demodulator VCC = 3.
To operate this way, the user must make sure that the "0" and "1" level at the output of the discriminator are "on both sides" of the comparison level in order for the decision to be made properly. Figure 22.
AT86RF211 Transmitter Description Figure 23. Typical Expected Currents in Tx Mode Supply Current - Tx Mode 65.00 915MHz 868MHz 60.00 55.00 Isupply (mA) 50.00 433MHz 45.00 40.00 35.00 30.00 25.00 20.00 15.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 Vsupply (V) Detailed Current - Tx Mode 30.00 PA Supply Currents (mA) 25.00 20.00 TXVCC 15.00 EVCC2 10.00 EVCC1 5.00 CVCC2 CVCC1 RXVCC DIVCC 0.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.
Power Amplification The Power Amplifier has been built to deliver more than +10 dBm, i.e. 10 mW in the three popular frequency bands. This power level is intended to be measured on the aerial port with a correct output matching network. Note that a correct calculation of the matching network guarantees an optimal power efficiency. Naturally, the greater the PA output voltage swing, the better the power efficiency. As the PA output is supplied through an inductor, a swing of 2 x VDD is possible.
AT86RF211 An automatic level control loop (ALC) is integrated, in order to minimize the sensitivity of the PA to the temperature, process and power supply variations. For instance, at +85°C, the output power is about 2 dB less than at 25°C. At -40°C, the output power is higher than at 25°C. The ALC is controlled by a current which is generated in the following way: Figure 26. ALC of the Power Amplifier iref = (v) U 1.
Figure 28. RPOWER Input Schematic 100 Ω Note: Software Control RPOWER Keeping the PA output matched guarantees maximum power efficiency. The power can then be adjusted, from the value set by RPOWER down to a maximum of 12 dB below, by programming the bits 6 to 8 of the CTRL1 register. So, 8 levels are digitally selectable with a variation of the output power. The minimum regulated output power is set to -10 dBm. Table 3.
AT86RF211 • Register Interface Format A message is made of 3 fields: – address A[3:0]: 4 bits (MSB first) – R/W: read/write selection – data D[31:0]: up to 32 bits (MSB first) ADDRESS A[3] A[2] R/W A[1] A[0] DATA up to 32 bits (variable length) R/W MSB D[nbit-1:0] LSB Variable register length and partial read or write cycles are supported. In case of partial read or write cycles, the first data (in or out) is always the MSB of the register.
Only the 2 MSBs are updated on the rising edge of SLE; other register bits are unchanged. • READ Mode (R/W = 0) The address and R/W bits are clocked on the rising edge of SCK. The data bits are changed on the falling edge of SCK. The MSB of the register is the first bit read. SDATA I/O pin is switched from input to output on the edge following the "1" clocking the R/W bit. It is possible to stop reading a register (SLE back to “1”) at any time.
AT86RF211 Figure 33. Chronogram with Timing tdle tdle SLE T tw tw SCK tsd SDATA A[3] A[2] SDATA direction Note: thd A[1] tpzon A[0] R/W D[9 ] tpd tpzd D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] INPUT OUTPUT INPUT For the timing specification, please refer to the timing table “Digital CMOS DC Characteristics” on page 42. Registers Table 4.
Reset Register (RESET) Name RESET nbit 0 Writing in this register (0 or 1) triggers an asynchronous reset. This register can only be written. All registers return to reset state. The chip returns in power-down. So all the following blocks are reset: • All registers to default value • Wake-up function. • Clock recovery function. And with the power-down state, reset is applied to the following blocks: • Synthesizer dividers. • Clock recovery function. • PLL lock detect.
AT86RF211 Table 6.
Table 6. CTRL1 Detailed Description(1)(2)(4)(3) (Continued) Name Number of Bits – 1 reserved, must be kept to reset value: 0 RXFS 2 RX frequency selection (00)2: F0 (01)2: F1 Comments (10)2: F2 (11)2: F3 reset value: (10)2 XTALFQ 1 Crystal frequency 0: 10.245 MHz (when IF1 = 10.7 MHz) 1: 20.945 MHz (when IF1 = 21.
AT86RF211 Control Register (CTRL2) Table 7. CTRL2 Overview Name DATARATE DATATOL LDCK N0LD1 N1LD2 nbit 31-18 17-10 9 8-5 4-0 init (0000)16 (00)16 0 (0010)2 (10111)2 Register reset value = (00000057)16 Table 8. CTRL2 Detailed Description Name Number of bits DATARATE 14 Comments Received DATAMSG rate This value must be programmed to have the DATACLK activated. (selected with DATACLK bit in CTRL1 register).
If the tolerance is too high, the rate value is reached earlier, and the rate value could be unstable (too big step). If the tolerance is too low, it could be difficult to catch up the DATA and the function could get lost. Notice that maximum acceptable distance between two data transitions depends on the precision of DATARATE versus transmitter actual data rate. Synchronization mechanism is explained with the chronogram hereafter. The synchronization is done for the first bit.
AT86RF211 DATARATE[13:0] Rate Period (1067)10 9.6 kbps 1 bit ~ 1067 x T (2135)10 4.8 kbps 1 bit ~ 2135 x T (4269)10 2.4 kbps 1 bit ~ 4269 x T (10246)10 1 kbps 1 bit ~ 10246 x T • Datatol Programming The tolerance for the extraction of DATA rate must be nearly 2% of the RATE. The tolerance represents the step for the calculation of the rate. If the tolerance is too high, rate value is reached earlier but the rate value could be unstable (step too big).
Frequency Registers Table 9. Frequency Registers Name F0, F1, F2, F3 nbit 31-0 Name Number of bits F0 32 Frequency code value F0 default register in TX mode ("0" code in FSK modulation). F1 32 Frequency code value F1 default register in TX mode ("1" code frequency in FSK modulation). F2 32 Frequency code value F2 default register in RX mode. F3 32 Frequency code value F3 Note: Comments 1. F0, F1, F2 and F3 registers must be programmed before using the device.
AT86RF211 In reception mode, only one frequency needs to be programmed. In transmission mode, two different registers (F0 & F1), or (F2 & F3) must be programmed for “0” code and “1” code transmission. The DATAMSG pin value actually selects the used register. The four registers can also be set to define two channels, so that the AT86RF211 may switch quickly from a channel to the other. Mode Programmed Frequency RX FCHANNEL ± IF1 TX FCHANNEL ± deviation Example: FCHANNEL = 868.3 MHz IF1 = 10.
Table 11. Status Register Detailed Description Name Number of bits PLLL 1 Comments PLL Lock flag 0: PLL unlocked 1: PLL locked reset value: 0 MRSSI 6 Measured RSSI level reset value: (00)16 MVCC 6 Measured VCC power supply voltage or discriminator output when MOFFSET = 1 reset value: (00)16 WAKEUP 1 WAKEUP flag Copy of the WAKEUP pin, but not affected by polarity selection.
AT86RF211 Table 13. DTR Detailed Description Name Number of bits DSOFFSET 4 Comments Data Slicer reference tuning (0000)2 to (1111)2 reset value: (1000)2 DISCHIGH 1 Discriminator offset shift (high) 0: no shift 1: output level increased reset value: 0 DISCLOW 1 Discriminator offset shift (low) 0: no shift 1: output level decreased reset value: 0 Wake-up Control Register Table 14.
Table 15. WUC Detailed Description (Continued) Name Number of bits DATL 5 Comments Data length Valid in fixed data length mode (STOP = 0).
AT86RF211 Table 16.
• WL2 programming WL2 can be set as a multiple of WL1 from 0 to 31 WL1. Table 18. WL2 Programming WL2[2:0] Period Comments (000)2 0 Simultaneous test of the RSSI and the header (001)2 1 x WL1 (010)2 2 x WL1 (011)2 3 x WL1 (100)2 4 x WL1 (101)2 8 x WL1 (110)2 16 x WL1 (111)2 31 x WL1 Wake-up Data Rate Register (WUR) Table 19. WUR Overview Name WUOP RATECHK RATE RATETOL nbit 17-16 15 14-5 4-0 init (01)2 0 (0000010000)2 (01000)2 Table 20.
AT86RF211 The data rate (in bps) and the decimal value to be coded in the register are related by the equation: 640000 RATE = ------------------------rate (bps) The following table gives the programming values of commonly used rates: Rate WUR RATE 1200 bits/sec (533)10 2400 bits/sec (267)10 4800 bits/sec (133)10 9600 bits/sec (67)10 Wake Up Address Register (WUA) Table 21. WUA Overview Name ADDL ADD nbit 24-20 19-0 init (01001)2 (0f0f0)16 Table 22.
Wake-up Data Register (WUD) Table 23. WUD Overview Name WUD nbit (data length -1) - 0 Table 24. WUD Detailed Description Name Number of bits WUD Length Note: 40 Comments Wake-up message data Warning: The length of this register is variable: * case fixed data length (STOP = 0 of WUC) data length is given by DATL of WUC. * case variable data length (STOP = 1 of WUC) data length is given by MSGDATL of STAT register. Warning: The first bit of received data is the LSB: WUD[0].
AT86RF211 Electrical Specification ESD sensitive device: storage or handling of the device must be carried out according to usual protection rules. Absolute Maximum Ratings Temperature +95°C Storage temperature -65 to +150°C Supply voltage 0 to 3.95V Digital input voltage -0.3 to VCC + 0.3V RXIN input power 0 dBm Note: DC Characteristics Stresses beyond the conditions listed above may cause permanent damage to the device.
Digital CMOS DC Characteristics Unless otherwise specified, data is given for T = 25°C, VSUPPLY = 2.7V Name Parameter Vil CMOS low level input voltage - Normal input(2) - Schmitt trigger input(3) Vih CMOS high level input voltage - Normal input(2) - Schmitt trigger input(3) (1) Voh Min Typ Max Units 0.3*Vcc 0.2*Vcc V V 0.7*Vcc 0.85*Vcc CMOS low level output voltage(1) Vol Note: Conditions CMOS high level output voltage V V Iol = 1 mA Ioh = - 1 mA 0.2*Vcc 0.8*Vcc V V 1.
AT86RF211 Synthesizer Specification Unless otherwise specified, data is given for T = 25°C, VSUPPLY = 2.7V ii Parameter Min Frequency Range Max Unit Comments 400 480 MHz Digital programming Frequency Range 800 950 MHz Digital programming Crystal Frequency 10.235 10.245 10.255 MHz IF 1 = 10.7 MHz(1) Crystal Frequency 20.925 20.945 20.965 MHz IF 1 = 21.
Transmitter Specification Unless otherwise specified, data is given for T = 25°C, VSUPPLY = 2.7V, RPOWER = 18 kΩ.
AT86RF211 Typical Application Implementation Optional SAW Filter VCC VCC SAW VCC VCC VCC IF1 Filter: 10.7 MHz or 21.4 MHz Rpower ANTENNA IF2 Optional Ceramic Filter (455 kHz) AT86RF211 VCC Optional RC Filter VCC 10.245 MHz or 20.945 MHz Note: Accurate information about parts and values of components to be used around AT86RF211 are described in our application notes. "RF Bill-of-Material/cost for 868-915 MHz applications".
Layout Reference Design Top Layer Each unused area must be filled with copper and connected to the bottom side ground plane Decoupling capacitors remain close to the supply pins Reference Design Bottom Layer One-block ground plane with no slot under the whole RF area This small slot is allowed as it is under the RF211: thus there is no track above 46 AT86RF211 1942C–WIRE–06/02
AT86RF211 Packaging Information 48 lead TQFP Dimension Nominal Value (mm) Tolerance Dimension Nominal Value (inch) Tolerance A 1.60 max A 0.063 max A1 0.05 min/0.15 max A1 0.002 min/0.06 max A2 1.40 ±0.05 A2 0.055 ±0.002 D 9.00 ±0.20 D 0.354 ±0.008 D1 7.00 ±0.10 D1 0.275 ±0.004 E 9.00 ±0.20 E 0.354 ±0.008 E1 7.00 ±0.10 E1 0.275 ±0.004 L 0.60 +0.15/-0.10 L 0.024 +0.006/-0.004 e 0.50 basic e 0.020 basic b 0.22 ±0.05 b 0.009 ±0.002 ccc 0.
Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.