Manual

13
AT86RF401
1424D–RKE–09/02
During power-on reset and watchdog reset, all I/O registers are set to their initial values,
and the program starts execution from address $000.
Note: The instruction placed in address $000 must be an RJMP (relative jump) instruction or a
JMP (absolute jump) to the reset handling routine. If an RJMP or JMP instruction is not
present at address $000, the part is placed into a “no program” resetstate.Thisistopro-
tect the part from fetching instructions when no program is present.
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is a minimum of four
clock cycles. After the four clock cycles, the program vector address for the actual inter-
rupt handling routine is executed. During this four clock cycle period, the Program
Counter is pushed onto the stack. The vector is a jump to the interrupt routine, and this
jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter is popped back from the stack. When AVR exits from
an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note: The Status Register (SREG) is not saved by the AVR hardware. This must be performed
by user software when required.
Memory Programming
Program Memory Lock
Bits
The AT86RF401 microtransmitter provides two lock bits that can be left unprogrammed
(“1”) or can be programmed (“0”) to obtain the additional features listed in Table 5.
Note: The lock bits can only be erased with the Chip Erase operation.
In-system Flash and
EEPROM
The AT86RF401 offers 2 Kbytes (1K x 16) of in-system reprogrammable Flash program
memory and 128 bytes of EEPROM data memory. This memory can be programmed
serially via the SPI interface.
SPI Interface Both the program and data memory arrays can be programmed using the serial SPI bus
while RESETB is pulled to GND. The serial interface consists of pins SCK, SDI (input)
and SDO (output).
When programming, an auto-erase cycle is built into the self-timed programming opera-
tion, and there is no need to first execute the Chip Erase instruction. The Chip Erase
operation sets every memory location in the EEPROM array to $FF.
Either an external system clock is supplied at pin XTAL/CLK or a crystal needs to be
connected across pins XTAL/CLK and XTALB. The minimum low and high periods for
the serial clock (SCK) input are defined as follows:
Low: 4 XTAL Clock Cycles High: 16 XTAL Clock Cycles
Table 5. Lock Bit Protection Modes
Program Lock Bits
Protection Type
Mod
e
LB1 LB2
1 1 1 No program lock features
201
Further programming of the EEPROM is disabled (both program and
data memory).
3 0 0 Same as mode 2, but Verify is also disabled