Manual

17
AT86RF401
1424D–RKE–09/02
Figure 6. AVR Core Architecture
The AVR uses a Harvard architecture concept, with separate memories and buses for
program and data. The program memory is executed with a two-stage pipeline. While
one instruction is being executed, the next instruction is prefetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The pro-
gram memory is in-system, reprogrammable Flash memory.
With the jump and call instructions, the whole 1K word address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 7-bit stack pointer SP is read/write accessible in the I/O
space.
The 128-byte data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
1K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Control
Bit Timer
SPI Unit
Programmable
Clock Divider
128 x 8
EEPROM
Data Bus 8-bit
Brown-out/Low
Battery Detector
128 x 8
Data
SRAM
Direct Addressing
Indirect Addressing
RF
Transmitter
Watchdog
Timer
6
I/O Lines