User Manual

13
AT8xC5122/23
4202E–SCR–06/06
Pin Description
Table 2. Pin Description
Port
VQFP64 VQFP32 PLCC68 PLCC28
QFN64 QFN32
Internal
Power
Supply ESD I/O
Reset
Level Alt
Reset
Config Conf 1 Conf 2 Conf 3 Led
P0.0 30 - 41 - 30 - VCC 2KV I/O Float AD0 P0 KB_OUT Push-pull
P0.1 29 - 40 - 29 - VCC 2KV I/O Float AD1 P0 KB_OUT Push-pull
P0.2 28 - 39 - 28 - VCC 2KV I/O Float AD2 P0 KB_OUT Push-pull
P0.3 27 - 38 - 27 - VCC 2KV I/O Float AD3 P0 KB_OUT Push-pull
P0.4 25 - 36 - 25 - VCC 2KV I/O Float AD4 P0 KB_OUT Push-pull
P0.5 24 - 35 - 24 - VCC 2KV I/O Float AD5 P0 KB_OUT Push-pull
P0.6 23 - 34 - 23 - VCC 2KV I/O Float AD6 P0 KB_OUT Push-pull
P0.7 22 - 33 - 22 - VCC 2KV I/O Float AD7 P0 KB_OUT Push-pull
CIO 64 32 9 4 64 32 CVCC 6KV I/O 0 Port51
CVCC inactive at reset.
ESD tested with a 10µF on CVCC
An external pull-up of 10K is
recommended to support ICC’s
with too high internal pull-ups.
CC4 3 3 12 7 3 3 CVCC 6KV I/O 0 Port51
CVCC inactive at reset
ESD tested with a 10µF on CVCC
P1.2 2 2 11 6 2 2 VCC 2KV I/O 1 CPRES Port51
Weak & medium pull-up can be
disconnected
CC4 9 5 18 9 9 5 CVCC 6KV I/O 0 Port51
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CCLK 12 6 21 10 12 6 CVCC 6KV O 0 Push-pull
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CRST 6 4 15 8 6 4 CVCC 6KV O 0 Push-pull
CVCC inactive at reset
ESD tested with a 10µF on CVCC
P1.6 47 23 58 - 47 23 VCC 2KV I/O 1 SS Port51
P1.7 62 31 7 - 62 31 VCC 2KV I/O 1 CCLK1 Port51
P2.0 58 - 3 - 58 - VCC 2KV I/O 1 A8 Port51 Push-pull KB_OUT
Input
WPU
P2.1 57 - 2 - 57 - VCC 2KV I/O 1 A9 Port51 Push-pull KB_OUT
Input
WPU
P2.2 56 - 1 - 56 - VCC 2KV I/O 1 A10 Port51 Push-pull KB_OUT
Input
WPU
P2.3 52 - 65 - 52 - VCC 2KV I/O 1 A11 Port51 Push-pull KB_OUT
Input
WPU
P2.4 51 - 64 - 51 - VCC 2KV I/O 1 A12 Port51 Push-pull KB_OUT
Input
WPU
P2.5 50 - 63 - 50 - VCC 2KV I/O 1 A13 Port51 Push-pull KB_OUT
Input
WPU