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Features

• 8-bit Microcontroller Compatible with MCS

51 Products

• Enhanced 8051 Architecture

– Single Clock Cycle per Byte Fetch

– Up to 20 MIPS Throughput at 20 MHz Clock Frequency

– Fully Static Operation: 0 Hz to 20 MHz

– On-chip 2-cycle Hardware Multiplier

– 128 x 8 Internal RAM

– 4-level Interrupt Priority

• Nonvolatile Program Memory

– 2K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: Minimum 10,000 Write/Erase Cycles

– Data Retention: Minimum 10 Years

– Serial Interface for Program Downloading

– 32-byte Fast Page Programming Mode

– 64-byte User Signature Array

– 2-level Program Memory Lock for Software Security

• Peripheral Features

– Two 16-bit Enhanced Timer/Counters

– Two 8-bit PWM Outputs (AT89LP213 only)

– Enhanced UART with Automatic Address Recognition and Framing Error

Detection (AT89LP214 only)

– Enhanced Master/Slave SPI with Double-buffered Send/Receive

– Programmable Watchdog Timer with Software Reset

– Analog Comparator with Selectable Interrupt and Debouncing

– 8 General-purpose Interrupt Pins

• Special Microcontroller Features

– Two-wire On-chip Debug Interface

– Brown-out Detection and Power-on Reset with Power-off Flag

– Internal RC Oscillator

– Low Power Idle and Power-down Modes

– Interrupt Recovery from Power-down Mode

• I/O and Packages

– Up to 12 Programmable I/O Lines

– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and

Open-drain Modes

– 5V Tolerant I/O

– 14-lead TSSOP or PDIP

• Operating Conditions

– 2.4V to 5.5V V

Voltage Range

–-40° C to 85°C Temperature Range

1. Description

The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller

with 2K bytes of In-System Programmable Flash memory. The device is manufactured

using Atmel's high-density nonvolatile memory technology and is compatible with the

industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an

enhanced CPU core that can fetch a single byte from memory every clock cycle.

In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-

tions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions

need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the stan-

dard 8051. Seventy percent of instructions need only as many clock cycles as they

8-bit

Microcontroller

with 2K Bytes

Flash

AT89LP213

AT89LP214

Preliminary

3538A–MICRO–7/06

Summary of content (90 pages)

PAGE 1
Features • 8-bit Microcontroller Compatible with MCS®51 Products • Enhanced 8051 Architecture • • • • • – Single Clock Cycle per Byte Fetch – Up to 20 MIPS Throughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier – 128 x 8 Internal RAM – 4-level Interrupt Priority Nonvolatile Program Memory – 2K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: Minimum 10,000 Write/Erase Cycles – Data Retention: Minimum 10 Years – Serial Interfac
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have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption.
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AT89LP213/214 [Preliminary] 3. Pin Description Table 3-1. Pin 1 AT89LP213 Pin Description Symbol P1.5 Type I/O I/O I 2 P1.7 I/O I/O I Description P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI5: General-purpose Interrupt input 5. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output.
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Table 3-2. Pin 1 AT89LP214 Pin Description Symbol P1.5 Type I/O I/O I 2 P1.7 I/O I/O I P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI5: General-purpose Interrupt input 5. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI7: General-purpose Interrupt input 7. 3 P1.
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AT89LP213/214 [Preliminary] 4. Block Diagram Figure 4-1. AT89LP213 Block Diagram Single Cycle 8051 CPU SPI 2KB Flash Timer 0 Timer 1 128 Bytes RAM Analog Comparator Port 3 Configurable I/O Watchdog Timer Port 1 Configurable I/O On-Chip RC Oscillator CPU Clock General-purpose Interrupt Figure 4-2.
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5. Comparison to Standard 8051 The AT89LP213/214 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051.
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AT89LP213/214 [Preliminary] 5.6 Watchdog Timer The Watchdog Timer in AT89LP213/214 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the counting rate. 5.7 I/O Ports The I/O ports of the AT89LP213/214 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset.
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A map of the AT89LP213/214 program memory is shown in Figure 6-1. In addition to the 2K code space from 0000h to 07FFh, the AT89LP213/214 also supports a 64-byte User Signature Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fashion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays.
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AT89LP213/214 [Preliminary] 7. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 7-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
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8. Enhanced CPU The AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz.
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AT89LP213/214 [Preliminary] Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data) T1 T2 T3 System Clock Total Execution Time Fetch Immediate Operand ALU Operation Execute Result Write Back Fetch Next Instruction 8.1 Restrictions on Certain Instructions The AT89LP213/214 is an economical and cost-effective member of Atmel's growing family of microcontrollers. It contains 2K bytes of Flash program memory.
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9. System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The clock source is selected by the Clock Source User Fuses as shown in Table 9-1. No internal clock division is used to generate the CPU clock from the system clock. See “User Configuration Fuses” on page 71. Table 9-1. 9.
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AT89LP213/214 [Preliminary] Table 9-2. CLKREG – Clock Control Register CLKREG = 8FH Reset Value = 0000 0000B Not Bit Addressable Bit Symbol TPS3 TPS2 TPS1 TPS0 TPS3 TPS2 TPS1 TPS0 – CDV1 CDV0 COE 7 6 5 4 3 2 1 0 Function Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The prescaler is implemented as a 4-bit binary down counter.
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Figure 10-1. Power-on Reset Sequence (BOD Disabled) VPOR VCC VPOR tPOR + tSUT TIME-OUT RST (RST Tied to VCC) INTERNAL RESET RST VRH (RST Controlled Externally) INTERNAL RESET tRHD If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after VCC reaches the BOD threshold voltage VBOD as shown in Figure 10-2.
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AT89LP213/214 [Preliminary] Table 10-1. Start-up Timer Settings SUT Fuse 1 SUT Fuse 0 0 0 0 tSUT (± 5%) Internal RC/External Clock 16 µs Crystal Oscillator 1024 µs Internal RC/External Clock 512 µs Crystal Oscillator 2048 µs Internal RC/External Clock 1024 µs Crystal Oscillator 4096 µs Internal RC/External Clock 4096 µs Crystal Oscillator 16384 µs 1 1 0 1 10.
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10.4 Watchdog Reset When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times out. See “Programmable Watchdog Timer” on page 57 for details on the operation of the Watchdog. 10.
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AT89LP213/214 [Preliminary] begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page 15). The interrupt pin need not remain low for the entire time-out period. Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0) PWD XTAL1 tSUT INT1 INTERNAL CLOCK When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, power-down is exited and the oscillator is restarted.
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Figure 11-3. Reset Recovery from Power-down. PWD XTAL1 tSUT RST INTERNAL CLOCK INTERNAL RESET Table 11-1. PCON – Power Control Register PCON = 87H Reset Value = 000X 0000B Not Bit Addressable Bit SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 Symbol Function SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3. SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE.
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AT89LP213/214 [Preliminary] instruction, an internal polling sequence determines which request is serviced. The polling sequence is based on the vector address; an interrupt with a lower vector address has higher priority than an interrupt with a higher vector address. Note that the polling sequence is only used to resolve pending requests of the same priority level. The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated, depending on bits IT0 and IT1 in Register TCON.
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12.1 Interrupt Response Time The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress.
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AT89LP213/214 [Preliminary] Table 12-2. IE – Interrupt Enable Register IE = A8H Reset Value = 0000 0000B Bit Addressable Bit EA EC EGP ES ET1 EX1 ET0 EX0 7 6 5 4 3 2 1 0 Symbol Function EA Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled by setting /clearing its own enable bit.
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Table 12-4. IPH – Interrupt Priority High Register IPH = B7H Reset Value = X000 0000B Not Bit Addressable Bit – – PGH PSH PT1H PX1H PT0H PX0H 7 6 5 4 3 2 1 0 Symbol Function PGH General-purpose Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High 13.
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AT89LP213/214 [Preliminary] . Table 13-2. 13.1.1 Configuration Modes for Port x, Bit y PxM0.y PxM1.y Port Mode 0 0 Quasi-bidirectional 0 1 Push-pull Output 1 0 Input Only (High Impedance) 1 1 Open-drain Output Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasibidirectional port can be used both as an input and output without the need to reconfigure the port.
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13.1.2 Input-only Mode The input only port configuration is shown in Figure 13-2. The output drivers are tristated. The input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Input pins can be safely driven to 5.5V even when operating at lower VCC levels; however, the input threshold of the Schmitt trigger will be set by the VCC level and must be taken into consideration. Figure 13-2.
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AT89LP213/214 [Preliminary] Figure 13-5. Push-pull Output VCC Port Pin From Port Register Input Data PWD 13.2 Port 1 Analog Functions The AT89LP213/214 incorporates an analog comparator. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in “Port Configuration” on page 22.
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13.4 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP213/214 share functionality with the various I/Os needed for the peripheral units. Table 13-5 lists the alternate functions of the port pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “0”.
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AT89LP213/214 [Preliminary] 14. Enhanced Timer/Counters The AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Timer, the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 9-2 on page 13). Both Timers share the same prescaler.
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Figure 14-1. Timer/Counter 1 Mode 0: Variable Width Counter OSC ÷TPS C/T = 0 TL1 (8 Bits) C/T = 1 T1 Pin Control PSC1 TR1 TH1 (8 Bits) GATE Interrupt TF1 INT1 Pin Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace the corresponding Timer 1 signals in Figure 14-1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). The INT0 and INT1 pins are shared with the XTAL oscillator.
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AT89LP213/214 [Preliminary] 14.3 Mode 2 – 8-bit Auto-reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 14-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.
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. Table 14-1. TCON – Timer/Counter Control Register TCON = 88H Reset Value = 0000 0000B Bit Addressable Bit TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 7 6 5 4 3 2 1 0 Symbol Function TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine. TR1 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off. TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
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AT89LP213/214 [Preliminary] Table 14-2. TMOD: Timer/Counter Mode Control Register TMOD = 88H Reset Value = 0000 0000B Not Bit Addressable GATE C/T M1 M0 GATE C/T M1 M0 7 6 5 4 3 2 1 0 Timer1 Timer0 Gate Gating control when set. Timer/Counter x is enabled only while INTx pin is high and TRx control pin is set. When cleared, Timer x is enabled whenever TRx control bit is set.
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. Table 14-3. TCONB – Timer/Counter Control Register B TCONB = 91H Reset Value = 0010 0100B Not Bit Addressable Bit PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02 PSC01 PSC00 7 6 5 4 3 2 1 0 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4). PSC12 PSC11 PSC10 Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1.
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AT89LP213/214 [Preliminary] 14.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see Figure 14-6). The PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 0.
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Figure 14-7. Timer/Counter 1 PWM Mode 1 RH1 (8 Bits) RL1 (8 Bits) OCR1 = T1 OSC TH1 (8 Bits) TL1 (8 Bits) ÷TPS Control TR1 GATE INT1 Pin 14.5.3 Mode 2 – 8-bit Frequency Generator Timer 0 in PWM Mode 2 functions as an 8-bit auto-reload timer, the same as normal Mode 2, with the exception that the output pin T0 is toggled at every TL0 overflow (see Figure 14-8). Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be used to output a square wave of varying frequency.
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AT89LP213/214 [Preliminary] 14.5.4 Mode 3 – Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate PWM counters in a manner similar to normal Mode 3. PWM Mode 3 on Timer 0 is shown in Figure 14-9. Only the Timer Prescaler is available to change the output frequency during PWM Mode 3. TL0 can use the Timer 0 control bits: GATE, TR0, INT0, PWM0EN and TF0.
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15. External Interrupts When the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered.
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AT89LP213/214 [Preliminary] Table 16-2. GPLS – General-purpose Interrupt Level Select Register GPLS = 9BH Reset Value = 0000 0000B Not Bit Addressable GPLS7 GPLS6 GPLS5 GPLS4 GPLS3 GPLS2 GPLS1 GPLS0 7 6 5 4 3 2 1 0 Bit GPMOD.x 0 = detect low level or negative edge on P1.x 1 = detect high level or positive edge on P1.x . Table 16-3.
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17. Serial Interface The serial interface on the AT89LP214 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full Duplex Operation • 8 or 9 Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 • Interrupt on Receive Buffer Full or Transmission Complete The serial interface is full duplex, which means it can transmit and receive simultaneously.
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AT89LP213/214 [Preliminary] bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. The SM2 bit has no effect in Mode 0 but can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received. Table 17-1.
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17.2 Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation: Oscillator Frequency Mode 0 Baud Rate = ------------------------------------------------------2 The baud rate in Mode 2 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset), the baud rate is 1/32 of the oscillator frequency.
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AT89LP213/214 [Preliminary] 17.3 More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. Figure 17-1 on page 42 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register.
PAGE 42
Figure 17-1.
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AT89LP213/214 [Preliminary] 17.4 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP214, the baud rate is determined by the Timer 1 overflow rate. Figure 17-2 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive.
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Figure 17-2. Serial Port Mode 1 TIMER 1 OVERFLOW INTERNAL BUS “1” WRITE TO SBUF ÷2 SMOD1 =1 SMOD1 =0 S D Q CL SBUF TXD ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI SERIAL PORT INTERRUPT ÷16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG.
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AT89LP213/214 [Preliminary] 17.5 More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of “0” or “1”. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.
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Figure 17-3.
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AT89LP213/214 [Preliminary] Figure 17-4. Serial Port Mode 3 TIMER 1 OVERFLOW INTERNAL BUS TB8 WRITE TO SBUF ÷2 SMOD1 = 1 SMOD1 = 0 S D Q CL SBUF TXD ZERO DETECTOR ÷16 SHIFT DATA START STOP BIT TX CONTROL RX CLOCK SEND TI SERIAL PORT INTERRUPT ÷16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG.
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17.6 Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.
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AT89LP213/214 [Preliminary] In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example, the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110.
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The interconnection between master and slave CPUs with SPI is shown in Figure 18-1. The four pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.
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AT89LP213/214 [Preliminary] Table 18-1. SPCR – SPI Control Register SPCR Address = E9H Reset Value = 0000 0000B Not Bit Addressable Bit SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 7 6 5 4 3 2 1 0 Symbol Function SPIE SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPE SPI enable.
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Table 18-3. SPSR – SPI Status Register SPSR Address = E8H Reset Value = 000X X000B Not Bit Addressable Bit SPIF WCOL LDEN – – SSIG DISSO ENH 7 6 5 4 3 2 1 0 Symbol Function SPIF SP interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES = 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register. WCOL When ENH = 0: Write collision flag.
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AT89LP213/214 [Preliminary] Figure 18-2. SPI Shift Register Diagram 7 Serial In Serial Master 8 2:1 MUX D Serial Slave 2:1 MUX Q D LATCH Q Serial Out LATCH CLK CLK 8 Parallel Master Transmit Byte Parallel Slave (Write Buffer) 8 D (Read Buffer) 8 Q D LATCH 8 Q Receive Byte LATCH CLK CLK Figure 18-3. SPI Block Diagram S Oscillator MSB LSB Pin Control Logic Read Data Buffer Divider ÷4÷8÷32÷64 Write Data Buffer Clock SPI Clock (Mater) SCK 1.
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The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate = baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possible clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL determine which format is used for transmission.
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AT89LP213/214 [Preliminary] 19. Analog Comparator A single analog comparator is provided on the AT89LP213/214. The analog comparator has the following features: • Comparator Output Flag and Interrupt • Selectable Interrupt Condition – High- or Low-level – Rising- or Falling-edge – Output Toggle • Hardware Debouncing Modes Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1.1). Otherwise the output is a zero.
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Table 19-1. ACSR – Analog Comparator Control & Status Register ACSR = 97H Reset Value = XXX0 0000B Not Bit Addressable Bit – – CIDL CF CEN CM3 CM1 CM0 7 6 5 4 3 2 1 0 Symbol Function CIDL Comparator Idle Enable. If CIDL = 1 the comparator will continue to operate during Idle mode. If CIDL = 0 the comparator is powered down during Idle mode. The comparator is always shut down during Power-down mode. CF Comparator Interrupt Flag.
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AT89LP213/214 [Preliminary] 20. Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by triggering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K clock cycles.
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20.1 Software Reset A Software Reset of the AT89LP213/214 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set.
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AT89LP213/214 [Preliminary] 21. Instruction Set Summary The AT89LP213/214 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP213/214 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP213/214 may take 1, 2, 3 or 4 clock cycles to complete. The execution times of most instructions may be computed using Table 21-1. Table 21-1.
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Table 21-1.
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AT89LP213/214 [Preliminary] Table 21-1.
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Table 21-1.
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AT89LP213/214 [Preliminary] 22. On-chip Debug System The AT89LP213/214 On-chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory.
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22.2 Software Breakpoints The AT89LP213/214 microcontroller includes a BREAK instruction for implementing program memory breakpoints in software. A software breakpoint can be inserted manually by placing the BREAK instruction in the program code. Some emulator systems may allow for automatic insertion/deletion of software breakpoints. The Flash memory must be re-programmed each time a software breakpoint is changed.
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AT89LP213/214 [Preliminary] 23. Programming the Flash Memory The Atmel AT89LP213/214 microcontroller features 2KB of on-chip In-System Programmable Flash program memory. In-System Programming (ISP) allows programming and reprogramming of the microcontroller positioned inside the end system. Using a simple 4-wire SPI interface, the In-System programmer communicates serially with the AT89LP213/214 microcontroller, reprogramming all nonvolatile memories on the chip.
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The In-System Programming Interface is the only means of externally programming the AT89LP213/214 microcontroller. The ISP Interface can be used to program the device both insystem and in a stand-alone serial programmer. The ISP Interface does not require any clock other than SCK and is not limited by the system clock frequency. During In-System programming the system clock source of the target device can operate normally.
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AT89LP213/214 [Preliminary] Figure 23-2. AT89LP213/214 Memory Organization User Fuse Row Page 0 User Signature Array Page 1 Atmel Signature Array Page 0 Page 0 07FF Page 63 Page 62 Code Memory Page 1 Page 0 00 23.3 0000 1F Command Format Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H.
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Figure 23-3. Command Sequence Flow Chart Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Data Address +1 Figure 23-4.
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AT89LP213/214 [Preliminary] Table 23-2. Programming Command Summary Command Opcode Addr High Addr Low Data 0 Data n Program Enable(1) 1010 1100 0101 0011 – – – Chip Erase 1000 1010 – – – – Read Status 0110 0000 xxxx xxxx xxxx xxxx Status Out Load Page Buffer(2) 0101 0001 xxxx xxxx xxxb bbbb DataIn 0 ... DataIn n Write Code Page(2) 0101 0000 xxxx xaaa aaab bbbb DataIn 0 ... DataIn n Write Code Page with Auto-Erase(2) 0111 0000 xxxx xaaa aaab bbbb DataIn 0 ...
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23.4 Status Register The current state of the memory may be accessed by reading the status register. The status register is shown in Table 23-3. Table 23-3. Bit Status Register – – – – LOAD SUCCESS WRTINH BUSY 7 6 5 4 3 2 1 0 Symbol Function LOAD Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that the page buffer was previously loaded with data by the load page buffer command. SUCCESS Success flag.
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AT89LP213/214 [Preliminary] 23.7 User Configuration Fuses The AT89LP213/214 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in Table 23-5. Fuses are cleared by programming 00h to their locations. Programming FFh to fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command.
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23.8 Programming Interface Timing This section details general system timing sequences and constraints for entering or exiting InSystem Programming as well as parameters related to the Serial Peripheral Interface during ISP. The general timing parameters for the following waveform figures are listed in Section 23.8.6 ”Timing Parameters” on page 75. 23.8.1 Power-up Sequence Execute this sequence to enter programming mode immediately after power-up.
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AT89LP213/214 [Preliminary] 23.8.3 ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-on Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait tRLZ + tSTL. 4. Start programming session. Figure 23-7. In-System Programming (ISP) Start Sequence tRLZ VCC XTAL1 RST tSTL SS tZSS tSSE SCK 23.8.4 MISO HIGH Z MOSI HIGH Z ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1.
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23.8.5 Serial Peripheral Interface The Serial Peripheral Interface (SPI) is a byte-oriented full duplex synchronous serial communication channel. During In-System programming the programmer always acts as the SPI master and the target device always acts as the SPI slave. The target device receives serial data on MOSI and outputs serial data on MISO.
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AT89LP213/214 [Preliminary] 23.8.6 Timing Parameters The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10 are shown in Table 23-6. Table 23-6.
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24. Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +5.5V Maximum Operating Voltage ............................................ 5.5V DC Output Current...................................................... 15.0 mA 24.
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AT89LP213/214 [Preliminary] 24.3 Serial Peripheral Interface Timing Table 24-1. SPI Master Characteristics Symbol Parameter Min tCLCL Oscillator Period 41.
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Figure 24-1. SPI Master Timing (CPHA = 0) SS tSCK SCK (CPOL = 0) SCK (CPOL = 1) tSR tSF tSHSL tSLSH tSLSH tSHSL tSIS tSIH MISO tSOH tSOV MOSI Figure 24-2. SPI Slave Timing (CPHA = 0) SS tSCK tSSE SCK (CPOL = 0) SCK (CPOL= 1) tSR tSHSL tSLSH tSLSH tSHSL tSOV tSOE tSSD tSF tSOX tSOH MISO tSIS tSIH MOSI Figure 24-3.
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AT89LP213/214 [Preliminary] Figure 24-4. SPI Slave Timing (CPHA = 1) SS tSCK tSSE SCK (CPOL = 0) SCK (CPOL = 1) tSR tSF tSHSL tSLSH tSLSH tSHSL tSOE tSOV tSSD tSOX tSOH MISO tSIS tSIH MOSI 24.4 External Clock Drive Figure 24-5. External Clock Drive Waveform VCC = 2.4V to 5.
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24.5 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 2.4V to 5.5V and Load Capacitance = 80 pF. Variable Oscillator Symbol Parameter Min Max Units tXLXL Serial Port Clock Cycle Time 2tCLCL -15 µs tQVXH Output Data Setup to Clock Rising Edge tCLCL -15 ns tXHQX Output Data Hold after Clock Rising Edge tCLCL -15 ns tXHDX Input Data Hold after Clock Rising Edge 0 ns tXHDV Input Data Valid to Clock Rising Edge 15 ns Figure 24-6.
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AT89LP213/214 [Preliminary] 24.6.3 ICC Test Condition, Active Mode, All Other Pins are Disconnected VCC ICC RST XTAL2 (NC) CLOCK SIGNAL 24.6.4 VCC XTAL1 VSS ICC Test Condition, Idle Mode, All Other Pins are Disconnected VCC ICC RST XTAL2 (NC) CLOCK SIGNAL 24.6.5 VCC XTAL1 VSS Clock Signal Waveform for ICC Tests in Active and Idle Modes, tCLCH = tCHCL = 5 ns VCC - 0.5V 0.45V 0.7 VCC tCHCX 0.2 VCC - 0.1V tCHCL tCLCH tCHCX tCLCL 24.6.
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25. Ordering Information 25.1 Standard Package Speed (MHz) 20 25.2 Ordering Code Package AT89LP213-20PI AT89LP213-20XI 14P3 14X AT89LP214-20PI AT89LP214-20XI 14P3 14X 2.4V to 5.5V Operation Range Industrial (-40° C to 85° C) Green Package Option (Pb/Halide-free) Speed (MHz) 20 Power Supply Power Supply Ordering Code Package AT89LP213-20PU AT89LP213-20XU 14P3 14X AT89LP214-20PU AT89LP214-20XU 14P3 14X 2.4V to 5.
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AT89LP213/214 [Preliminary] 26. Packaging Information 26.1 14P3 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 18.669 – 19.685 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.
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26.2 14X – TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 5.10 (0.201) 4.90 (0.193) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º~ 8º 0.75 (0.030) 0.45 (0.018) 05/16/01 R 84 2325 Orchard Parkway San Jose, CA 95131 TITLE 14X (Formerly "14T"), 14-lead (4.
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AT89LP213/214 [Preliminary] 27. Revision History Revision No.
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AT89LP213/214 [Preliminary] 3538A–MICRO–7/06
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AT89LP213/214 [Preliminary] Table of Contents 1. Description ............................................................................................... 1 2. Pin Configuration ..................................................................................... 2 2.1 AT89LP213: 14-lead TSSOP/PDIP ......................................................................2 2.2 AT89LP214: 14-lead TSSOP/PDIP ......................................................................2 3. Pin Description .....
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Table of Contents (Continued) 11. Power Saving Modes ............................................................................. 16 11.1 Idle Mode ...........................................................................................................16 11.2 Power-down Mode .............................................................................................16 12. Interrupts ................................................................................................ 18 12.
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AT89LP213/214 [Preliminary] Table of Contents (Continued) 22. On-Chip Debug System ......................................................................... 63 22.1 Physical Interface ...............................................................................................63 22.2 Software Breakpoints .........................................................................................64 22.3 Limitations of On-Chip Debug ............................................................................
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.