Manual

AT89LS53
4-277
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V
CC
= 2.7V to 6V and Load Capacitance = 80 pF.
Symbol Parameter
12 MHz Oscillator Variable Oscillator
Units
Min Max Min Max
t
XLXL
Serial Port Clock Cycle Time 1.0 12t
CLCL
µs
t
QVXH
Output Data Setup to Clock
Rising Edge
700 10t
CLCL
- 133 ns
t
XHQX
Output Data Hold After Clock
Rising Edge
50 2t
CLCL
- 117 ns
t
XHDX
Input Data Hold After Clock
Rising Edge
00ns
t
XHDV
Clock Rising Edge to Input Data
Valid
700 10t
CLCL
- 133 ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms
(1)
Notes: 1. AC Inputs during testing are driven at V
CC
- 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at V
IH
min. for a logic 1 and V
IL
max. for a logic 0.
Float Waveforms
(1)
Notes: 1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V
OH
/V
OL
level occurs.