Features • • • • • • • • • • • Compatible with MCS-51™ Products 8K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes Description The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and
Block Diagram P0.0 - P0.7 P2.0 - P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC GND RAM ADDR. REGISTER B REGISTER PORT 0 LATCH RAM QUICK FLASH PORT 2 LATCH STACK POINTER ACC BUFFER TMP1 TMP2 PROGRAM ADDRESS REGISTER PC INCREMENTER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PROGRAM COUNTER PSW PSEN ALE/PROG EA / VPP TIMING AND CONTROL INSTRUCTION REGISTER DPTR RST PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS OSC P1.0 - P1.7 2 AT89C52 P3.0 - P3.
AT89C52 The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory.
AT89C52 Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. new features. In that case, the reset or inactive values of the new bits will always be 0. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. Timer 0 and 1 Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.
AT89C52 Figure 1. Timer in Capture Mode ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTROL C/T2 = 1 TF2 TR2 CAPTURE T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow.
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0) ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTROL TR2 C/T2 = 1 RELOAD TIMER 2 INTERRUPT T2 PIN RCAP2H RCAP2L TF2 TRANSITION DETECTOR EXF2 T2EX PIN CONTROL EXEN2 Table 4. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit – – – – – – T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function – Not implemented, reserved for future T2OE Timer 2 Output Enable bit.
AT89C52 Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) (DOWN COUNTING RELOAD VALUE) 0FFH ÷12 OSC TOGGLE 0FFH EXF2 OVERFLOW C/T2 = 0 TH2 TL2 TF2 CONTROL TR2 C/T2 = 1 TIMER 2 INTERRUPT T2 PIN RCAP2H RCAP2L COUNT DIRECTION 1=UP 0=DOWN (UP COUNTING RELOAD VALUE) T2EX PIN Figure 4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ.
Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
AT89C52 Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alter nate fu nctio ns. It can b e programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.
Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 8.
AT89C52 Program Memory Lock Bits The AT89C52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features.
Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
AT89C52 Figure 9. Programming the Flash Memory Figure 10. Verifying the Flash Memory +5V +5V AT87F52 A0 - A7 ADDR. OOOOH/1FFFH P1 P2.0 - P2.4 AT87F52 VCC P0 A8 - A12 PGM DATA A0 - A7 ADDR. OOOOH/1FFFH A8 - A12 P2.7 ALE PROG P3.6 P2.0 - P2.4 P0 P2.7 SEE FLASH PROGRAMMING MODES TABLE PGM DATA (USE 10K PULLUPS) ALE P3.6 VIH P3.7 P3.7 XTAL2 VCC P2.6 P2.
Flash Programming and Verification Waveforms - High-voltage Mode (VPP=12V) PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.4 VERIFICATION ADDRESS tAVQV PORT 0 DATA IN tAVGL tDVGL tGHDX DATA OUT tGHAX ALE/PROG tSHGL tGLGH VPP tGHSL LOGIC 1 LOGIC 0 EA/VPP (2) tEHSH tEHQZ tELQV P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC Flash Programming and Verification Waveforms - Low-voltage Mode (VPP=5V) PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.
AT89C52 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
AT89C52 External Program Memory Read Cycle tLHLL ALE tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tPXIZ tLLAX tPXIX A0 - A7 PORT 0 tPLPH INSTR IN A0 - A7 tAVIV A8 - A15 PORT 2 A8 - A15 External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tLLAX tAVLL PORT 0 tRLDV tRLAZ A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 - P2.
External Data Memory Write Cycle tLHLL ALE tWHLH PSEN tLLWL WR tAVLL tLLAX tQVWX A0 - A7 FROM RI OR DPL PORT 0 tWLWH tQVWH DATA OUT tWHQX A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH External Clock Drive Waveforms tCHCX VCC - 0.5V tCHCX tCLCH tCHCL 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL External Clock Drive Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period tCHCX Min Max Units 0 24 MHz 41.
AT89C52 . Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.
Ordering Information Speed (MHz) Power Supply 12 5V ± 20% 16 20 24 5V ± 20% 5V ± 20% 5V ± 20% Ordering Code Package AT89C52-12AC AT89C52-12JC AT89C52-12PC AT89C52-12QC 44A 44J 40P6 44Q Commercial (0°C to 70°C) AT89C52-12AI AT89C52-12JI AT89C52-12PI AT89C52-12QI 44A 44J 40P6 44Q Industrial (-40°C to 85°C) AT89C52-16AC AT89C52-16JC AT89C52-16PC AT89C52-16QC 44A 44J 40P6 44Q Commercial (0°C to 70°C) AT89C52-16AI AT89C52-16JI AT89C52-16PI AT89C52-16QI 44A 44J 40P6 44Q Industrial (-40°C to
AT89C52 Packaging Information 44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flatpack (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC JEDEC STANDARD MS-026 ACB 12.21(0.478) SQ 11.75(0.458) PIN 1 ID 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC .045(1.14) X 45° .045(1.14) X 30° - 45° PIN NO. 1 IDENTIFY .630(16.0) .590(15.0) .656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .
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