Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 1.5 MIPS Throughput at 1.
AT90C8534 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. The AT90C8534 Block Diagram PA0 - PA6 INT1,0 PORTA DRIVERS EXTERNAL INTERRUPTS VCC GND DATA DIR. REG. PORTA DATA REGISTER PORTA 8-BIT DATA BUS AVCC ADIN5..
AT90C8534 The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Crystal Oscillators XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Note that XTAL2 should not be used to drive other components. Figure 2. Oscillator Connections Figure 3.
AT90C8534 The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program memory is executed with a single-level pipelining.
Figure 5. Memory Maps Program Memory Data Memory $000 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (4K x 16) $005F $0060 Internal SRAM (256 x 8) $015F $FFF A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory.
AT90C8534 General-purpose Register File Figure 6 shows the structure of the 32 general-purpose working registers in the CPU. Figure 6. AVR CPU General-purpose Working Registers 7 0 Addr.
ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories: arithmetic, logical and bit functions. Programmable Flash Program Memory The AT90C8534 contains 8K bytes of on-chip programmable Flash memory for program storage.
AT90C8534 The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented and incremented. The 32 general-purpose working registers, 64 I/O registers and the 256 bytes of internal data SRAM in the AT90C8534 are all accessible through all these addressing modes.
I/O Direct Figure 11. I/O Direct Addressing Operand address is contained in six bits of the instruction word. n is the destination or source register address. Data Direct Figure 12. Direct Data Addressing Data Space 20 19 31 OP 16 $0000 Rr/Rd 16 LSBs 15 0 $015F A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register.
AT90C8534 Data Indirect with Displacement Figure 13. Data Indirect with Displacement Data Space $0000 15 0 Y OR Z - REGISTER 15 10 OP 6 5 n 0 a $015F Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word. Data Indirect Figure 14. Data Indirect Addressing Data Space $0000 15 0 X, Y OR Z - REGISTER $015F Operand address is the contents of the X-, Y- or the Z-register.
Data Indirect with Pre-decrement Figure 15. Data Indirect Addressing with Pre-decrement Data Space $0000 15 0 X, Y OR Z - REGISTER -1 $015F The X-, Y- or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y- or the Z-register. Data Indirect with Post-increment Figure 16. Data Indirect Addressing with Post-increment Data Space $0000 15 0 X, Y OR Z - REGISTER 1 $015F The X-, Y- or the Z-register is incremented after the operation.
AT90C8534 Constant Addressing Using the LPM Instruction Figure 17. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing PROGRAM MEMORY $000 15 0 Z-REGISTER $7FF/$FFF Program execution continues at address contained by the Z-register (i.e.
Relative Program Addressing, RJMP And RCALL Figure 19. Relative Program Memory Addressing +1 Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047. EEPROM Data Memory The AT90C8534 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
AT90C8534 Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 21. Single Cycle ALU Operation T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22.
I/O Memory The I/O space definition of the AT90C8534 is shown in Table 1. Table 1.
AT90C8534 Status Register – SREG The AVR status register (SREG) at I/O space location $3F ($5F) is defined as: Bit 7 6 5 4 3 2 1 0 $3F ($5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
decremented by 2 when data is pushed onto the stack with subroutine RCALL and interrupt. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when data is popped from the stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The AT90C8534 provides six different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space.
AT90C8534 Reset During reset, all I/O registers are set to their initial values and the program counter is set to address $000. When reset is released, the program starts execution from this address. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations.
Figure 24. External Reset on Start-up VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Figure 25. External Reset during Operation Interrupt Handling The AT90C8534 has two 8-bit Interrupt Mask control registers; GIMSK (General Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
AT90C8534 General Interrupt Mask Register – GIMSK Bit 7 6 5 4 3 2 1 0 $3B ($5B) INT1 INT0 – – – – – – Read/Write R/W R/W R R R R R R Initial value 0 0 0 0 0 0 0 0 GIMSK • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The external interrupt is activated on falling or rising edge of the INT1 pin.
Timer/Counter Interrupt Mask Register – TIMSK Bit 7 6 5 4 3 2 1 0 $39 ($59) – – – – – TOIE1 – TOIE0 Read/Write R R R R R R/W R R/W Initial value 0 0 0 0 0 0 0 0 TIMSK • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90C8534 and always read as zero. • Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled.
AT90C8534 MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 $35 ($55) – SE SM – – ISC1 – ISC0 Read/Write R R/W R/W R R R/W R R/W Initial value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – Res: Reserved Bit This bit is reserved bits in the AT90C8534 and always reads as zero. • Bit 6 – SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed.
Power-down Mode When the SM bit is set (one), the SLEEP instruction makes the MCU enter the Power-down Mode. In this mode, the external oscillator is stopped, while the external interrupts continue operating. Only an external reset or an external edge interrupt on INT0 or INT1 can wake up the MCU. Note that if INT0 or INT1 is used for wake-up from Power-down Mode, the edge is remembered until the MCU wakes up.
AT90C8534 Figure 27. Timer/Counter0 Block Diagram TOIE0 7 CS00 CS01 T/C0 CONTROL REGISTER (TCCR0) CS02 TIMER INT. FLAG REGISTER (TIFR) TOV1 TIMER INT. MASK REGISTER (TIMSK) TOV0 TOIE1 8-BIT DATA BUS T/C0 OVERFLOW IRQ 0 TIMER/COUNTER0 (TCNT0) T/C CLK SOURCE CONTROL LOGIC CK Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 ($53) – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7..
Timer Counter0 – TCNT0 Bit 7 6 5 4 3 2 1 0 $32 ($52) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is selected, the Timer/Counter0 continues counting in the timer clock cycle following the write operation. 16-bit Timer/Counter1 Figure 28 shows the block diagram for Timer/Counter1.
AT90C8534 • Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 5. Clock 1 Prescale Select CS12 CS11 CS10 Description 0 0 0 Stop, Timer/Counter1 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 Reserved 1 1 1 Reserved The Stop condition provides a Timer Enable/Disable function.
EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 35 ms, depending on the VCC voltages. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
AT90C8534 • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2.
Analog-to-digital Converter Feature list: • 10-bit Resolution • ± 2 LSB Accuracy (AVcc = 3.3 - 6.0V) • 76 - 175 µs Conversion Time • Up to 13 kSPS • 6 Multiplexed Input Channels • Rail-to-rail Input Range • Free Run or Single Conversion Mode • Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The AT90C8534 features a 10-bit successive approximation ADC. The ADC is connected to a 6-channel Analog Multiplexer, which allows each of the pins ADIN5..0 to be used as an input for the ADC.
AT90C8534 A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be set to zero by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change.
Figure 31. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle number 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 26 1 2 ADC clock ADEN ADSC Hold strobe ADIF ADCH MSB of result ADCL LSB of result Dummy Conversion Second Conversion Actual Conversion Figure 32.
AT90C8534 Figure 33. ADC Timing Diagram, Free Run Conversion 11 Cycle number 12 13 1 2 ADC clock ADSC Hold strobe ADIF ADCH MSB of result ADCL LSB of result One Conversion Next Conversion Table 6.
ADC Multiplexer Select Register – ADMUX Bit 7 6 5 4 3 2 1 0 $07 ($27) – – – – – MUX2 MUX1 MUX0 Read/Write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 ADMUX • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90C8534 and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0 The value of these three bits selects which analog input 5 - 0 is connected to the ADC. Selections 110 and 111 are reserved and should not be used.
AT90C8534 the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI or CBI instructions are used. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. • Bits 2..0 – ADPS2..
ADC Noise Canceling Techniques Digital circuitry inside and outside the AT90C8534 generates EMI, which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the AT90C8534 and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2.
AT90C8534 ADC Characteristics TA = -40°C to 85°C Symbol Parameter Condition Min Typ Resolution Max Units 10 Bits Absolute Accuracy AVCC = 3.3 - 6.0V INL Integral Nonlinearity AVCC = 3.3 - 6.0V 1 LSB DNL Differential Nonlinearity AVCC = 3.3 - 6.0V 2 LSB Zero Error (Offset) AVCC = 3.3 - 6.0V 0.5 LSB Conversion Time 76 Clock Frequency 80 AVCC Analog Supply Voltage RREF Reference Input Resistance RAIN Analog Input Resistance Note: 2 LSB 175 µs 170 (1) VCC - 0.
Table 9. DDAn Effects on Port A Pins Note: DDAn PORTAn Comment 0 0 Tri-state (high-Z) 0 1 Tri-state (high-Z) 1 0 Push-pull Zero Output 1 1 Push-pull One Output n: 6, 5, …, 0, pin number. Memory Programming Program and Data Memory Lock Bits The AT90C8534 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 10. Table 10.
AT90C8534 Signal Names In this section, some pins of the AT90C8534 are referenced by signal names describing their function during parallel programming. See Figure 35 and Table 11. Pins not described in Table 11 are referenced by pin names. The XA1/XA0 pins determines the action executed when the XTAL1 pin is given a positive pulse. The coding is shown in Table 12. When pulsing WR or OE, the command loaded determines the action executed.
. Table 12. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash/EEPROM/Signature Byte Address (high or low address byte for Flash/EEPROM determined by BS) 0 1 Load Data (high or low data byte for Flash determined by BS) 1 0 Load Command 1 1 No Action, Idle Table 13.
AT90C8534 Programming the Flash A: Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS to “0” 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $0F) 4. Give XTAL1 a positive pulse. This loads the address high byte.
Figure 36. Programming the Flash Waveforms DATA $10 ADDR. HIGH ADDR. LOW DATA LOW XA1 XA0 BS XTAL1 WR RDY/BSY PEN OE Figure 37. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY PEN OE Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” for details on command and address loading): 1. A: Load Command “0000 0010”. 2. B: Load Address High Byte ($00 - $0F). 3. C: Load Address Low Byte ($00 - $FF). 4.
AT90C8534 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. B: Load Address High Byte ($00 - $01). 3. C: Load Address Low Byte ($00 - $FF). 4. D: Load Data Low Byte ($00 - $FF). 5. E: Write Data Low Byte.
Parallel Programming Characteristics Figure 38. Parallel Programming Timing tXLWL tXHXL XTAL1 tDVXH tXLDX tBVWL tWLWH WR tRHBX tWHRL Write Data & Contol (DATA, XA0/1, BS) RDY/BSY tWLRH tXLOL tOHDZ tOLDV Read OE DATA Table 14. Parallel Programming Characteristics TA = 25°C ± 10%, VCC = 5.
AT90C8534 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature ................................. -40°C to +105°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
External Clock Drive Waveforms Figure 39. External Clock VIH1 VIL1 External Clock Drive VCC = 3.3V to 6.0V 46 Symbol Parameter 1/tCLCL Oscillator Frequency Min Max Units 0 1.5 MHz tCLCL Clock Period 667 ns tCHCX High Time 267 ns tCLCX Low Time 267 ns tCLCH Rise Time 0.5 µs tCHCL Fall Time 0.
AT90C8534 Typical Characteristics The following charts show typical behavior. These data are characterized, but not tested. Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 40. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 80 70 TA = 25˚C 60 I OL (mA) 50 40 TA = 85˚C 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 41. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs.
Figure 42. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 20 I OL (mA) TA = 85˚C 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Figure 43. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 4 3 I OH (mA) TA = 85˚C 2 1 0 0 0.5 1 1.5 VOH (V) 48 AT90C8534 2 2.
AT90C8534 AT90C8534 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) … $11 ($
Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks Add Two Registers Add with Carry Two Registers Add Immediate to Word Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg.
AT90C8534 Instruction Set Summary (Continued) Mnemonic Operands DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, -X LD Rd, Y LD Rd, Y+ LD Rd, -Y LDD Rd, Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST -X, Rr ST Y, Rr ST Y+, Rr ST -Y, Rr STD Y+q, Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q, Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P, b CBI P, b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD
Ordering Information Speed (MHz) Power Supply Ordering Code Package 1.5 3.3 - 6.0V AT90C8534-1AC 48A Commercial (0°C to 70°C) 1.5 3.3 - 6.0V AT90C8534-1AI 48A Industrial (-40°C to 85°C) Package Type 48A 52 48-lead, Thin (1.
AT90C8534 Packaging Information 48A, 48-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 9.25(.364) SQ 8.75(.344) PIN 1 ID 0.27(0.011) 0.17(0.007) 0.50(0.020) BSC 7.1(0.280) SQ 6.9(0.272) 1.60(0.063) MAX 0.20(.008) 0.09(.003) 0˚ 7˚ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.
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