Owner manual

AT90C8534
25
Figure 27. Timer/Counter0 Block Diagram
Timer/Counter0 Control Register – TCCR0
•
Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read zero.
•
Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0
The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK
oscillator clock.
Bit 7 6 5 4 3 2 1 0
$33 ($53) –– – – –CS02 CS01 CS00 TCCR0
Read/Write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 4. Clock 0 Prescale Select
CS02 CS01 CS00 Description
0 0 0 Stop, Timer/Counter0 is stopped.
00 1CK
01 0CK/8
01 1CK/64
10 0CK/256
1 0 1 CK/1024
1 1 0 Reserved
1 1 1 Reserved
8-BIT DA
TA BUS
T/C0 CONTROL
REGISTER (TCCR0)
TIMER/COUNTER0
(TCNT0)
07
T/C CLK SOURCE
CONTROL
LOGIC
CS02
CS01 CS00
CK
T/C0 OVER-
FLOW IRQ
TIMER INT. MASK
REGISTER (TIMSK)
TOIE0
TOIE1
TIMER INT. FLAG
REGISTER (TIFR)
TOV0
TOV1