Owner manual

AT90C8534
40
.
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 5V between VCC and GND.
2. Set PEN, RESET and BS pins to “0” and wait at least 100 ns.
3. Set RESET to “1”. Any activity on BS within 100 ns after RESET is changed to a logical “1” will cause the device to
fail entering programming mode.
Chip Erase
The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until
the Flash and EEPROM have been completely erased. Chip Erase must be performed before the Flash and EEPROM is
reprogrammed.
Load Command “Chip Erase”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS to “0”.
3. Set PB(7:0) to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR
a t
WLWH_CE
wide negative pulse to execute Chip Erase. See Table 14 for t
WLWH_CE
value. Chip Erase does
not generate any activity on the RDY/BSY
pin.
Table 12. XA1 and XA0 Coding
XA1 XA0 Action when XTAL1 is Pulsed
0 0 Load Flash/EEPROM/Signature Byte Address (high or low address byte for Flash/EEPROM determined by BS)
0 1 Load Data (high or low data byte for Flash determined by BS)
1 0 Load Command
1 1 No Action, Idle
Table 13. Command Byte Coding
Command Byte Command Executed
1000 0000 Chip Erase
0010 0000 Write Lock Bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes
0000 0100 Read Lock Bits
0000 0010 Read Flash
0000 0011 Read EEPROM