Manual
Table Of Contents
- Features
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- EEPROM Data Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt FLAG Register – TIFR
- External Interrupt
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counter
- Watchdog Timer
- EEPROM Read/Write Access
- I/O Port B
- Memory Programming
- Electrical Characteristics
- Typical Characteristics
- AT90S2323/2343 Register Summary
- Ordering Information
- Packaging Information
11
AT90S/LS2323/2343
1004D–09/01
SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized.
Figure 9. SRAM Organization
The 224 data memory locations address the Register file, I/O memory and the data
SRAM. The first 96 locations address the Register file + I/O memory, and the next 128
locations address the data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the
register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data address space.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- and Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are used and decremented and
incremented.
The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data
SRAM in the AT90S2323/2343 are all directly accessible through all these addressing
modes.
Register File Data Address Space
R0 $00
R1 $01
R2 $02
……
R29 $1D
R30 $1E
R31 $1F
I/O Registers
$00 $20
$01 $21
$02 $22
……
$3D $5D
$3E $5E
$3F $5F
Internal SRAM
$60
$61
$62
…
$DD
$DE
$DF