Manual
Table Of Contents
- Features
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- EEPROM Data Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt FLAG Register – TIFR
- External Interrupt
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counter
- Watchdog Timer
- EEPROM Read/Write Access
- I/O Port B
- Memory Programming
- Electrical Characteristics
- Typical Characteristics
- AT90S2323/2343 Register Summary
- Ordering Information
- Packaging Information
40
AT90S/LS2323/2343
1004D–09/01
Table 16. High-voltage Serial Programming Instruction Set
Instruction
Instruction Format
Operation RemarksInstr.1 Instr.2 Instr.3 Instr.4
Chip Erase
PB0
PB1
PB2
0_1000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Wait t
WLWH_CE
after Instr.3 for
the Chip Erase cycle to finish.
Write Flash
High and Low
Address
PB0
PB1
PB2
0_0001_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_00aa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
Repeat Instr.2 for a new
256-byte page. Repeat Instr.3
for each new address.
Write Flash
Low Byte
PB0
PB1
PB2
0_ i i i i_i i i i _00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
Wait after Instr.3 until PB2
goes high. Repeat Instr.1,
Instr. 2 and Instr.3 for each
new address.
Write Flash
High Byte
PB0
PB1
PB2
0_ i i i i_i i i i _00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
0_0000_0000_00
Wait after Instr.3 until PB2
goes high. Repeat Instr.1,
Instr. 2 and Instr.3 for each
new address.
Read Flash
High and Low
Address
PB0
PB1
PB2
0_0000_0010_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_00aa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
Repeat Instr.2 and Instr.3 for
each new address.
Read Flash
Low Byte
PB0
PB1
PB2
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
o_oooo_ooox_xx
Repeat Instr.1 and Instr.2 for
each new address.
Read Flash
High Byte
PB0
PB1P
B2
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
o_oooo_ooox_xx
Repeat Instr.1 and Instr.2 for
each new address.
Write
EEPROM
Low Address
PB0
PB1
PB2
0_0001_0001_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0bbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
Repeat Instr.2 for each new
address.
Write
EEPROM
Byte
PB0
PB1
PB2
0_ i i i i_i i i i _00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
Wait after Instr.3 until PB2
goes high
Read
EEPROM
Low Address
PB0
PB1
PB2
0_0000_0011_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0bbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
Repeat Instr.2 for each new
address.
Read
EEPROM
Byte
PB0
PB1
PB2
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
o_oooo_ooox_xx
Repeat Instr.2 for each new
address
Write Fuse
Bits (AT90S/
LS2323)
PB0
PB1
PB2
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_11S1_111F_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait t
WLWH_PFB
after Instr.3 for
the Write Fuse bits cycle to
finish. Set S,F = “0” to
program, “1” to unprogram.
Write Fuse
Bits (AT90S/
LS2343)
PB0
PB1
PB2
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_11S1_111R_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait t
WLWH_PFB
after Instr.3 for
the Write Fuse bits cycle to
finish. Set S,R = “0” to
program, “1” to unprogram.
Write Lock
Bits
PB0
PB1
PB2
0_0010_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_1111_1211_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
Wait after Instr.4 until PB2
goes high. Write 2, 1 = “0” to
program the Lock bit.