Manual
Table Of Contents
- Features
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- EEPROM Data Memory
- SRAM Data Memory
- Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd and Rr
- I/O Direct
- Data Direct
- Data Indirect with Displacement
- Data Indirect
- Data Indirect with Pre- decrement
- Data Indirect with Post- increment
- Constant Addressing Using the LPM Instruction
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Watchdog Reset
- MCU Status Register – MCUSR
- Interrupt Handling
- General Interrupt Mask Register – GIMSK
- General Interrupt Flag Register – GIFR
- Timer/Counter Interrupt Mask Register – TIMSK
- Timer/Counter Interrupt FLAG Register – TIFR
- External Interrupt
- Interrupt Response Time
- MCU Control Register – MCUCR
- Sleep Modes
- Timer/Counter
- Watchdog Timer
- EEPROM Read/Write Access
- I/O Port B
- Memory Programming
- Electrical Characteristics
- Typical Characteristics
- AT90S2323/2343 Register Summary
- Ordering Information
- Packaging Information
46
AT90S/LS2323/2343
1004D–09/01
Low-voltage Serial Programming Characteristics
Figure 37. Low-voltage Serial Programming Timing
Table 20. Low-voltage Serial Programming Characteristics, T
A
= -40°C to 85°C, V
CC
=
2.7 - 6.0V (unless otherwise noted)
Symbol Parameter Min Typ Max Units
1/t
CLCL
Oscillator Frequency (V
CC
= 2.7 - 4.0V) 0 4.0 MHz
t
CLCL
Oscillator Period (V
CC
= 2.7 - 4.0V) 250.0 ns
1/t
CLCL
Oscillator Frequency (V
CC
= 4.0 - 6.0V) 0 8.0 MHz
t
CLCL
Oscillator Period (V
CC
= 4.0 - 6.0V) 125.0 ns
t
SHSL
SCK Pulse Width High 2.0 t
CLCL
ns
t
SLSH
SCK Pulse Width Low 2.0 t
CLCL
ns
t
OVSH
MOSI Setup to SCK High t
CLCL
ns
t
SHOX
MOSI Hold after SCK High 2.0 t
CLCL
ns
t
SLIV
SCK Low to MISO Valid 10.0 16.0 32.0 ns
Table 21. Minimum Wait Delay after the Chip Erase Instruction
Symbol 3.2V 3.6V 4.0V 5.0V
t
WD_ERASE
18 ms 14 ms 12 ms 8 ms
Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol 3.2V 3.6V 4.0V 5.0V
t
WD_PROG
9 ms 7 ms 6 ms 4 ms
MOSI
MISO
SCK
t
OVSH
t
SHSL
t
SLSH
t
SHOX
t
SLIV