Features • High-performance and Low-power AVR® 8-bit RISC Architecture • • • • • • • – 118 Powerful Instructions – Most Single Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz Data and Non-volatile Program Memory – 4K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of SRAM – 256 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Perip
Pin Configurations 32 31 30 29 28 27 26 25 PD2 (INT0) PD1 (TXD) PD0 (RXD) RESET PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) TQFP Top View 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 PC1 (ADC1) PC0 (ADC0) NC AGND AREF NC AVCC PB5 (SCK) (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 (OC1) PB1 (SS) PB2 (MOSI) PB3 (MISO) PB4 9 10 11 12 13 14 15 16 (INT1) PD3 (T0) PD4 NC VCC GND NC XTAL1 XTAL2 PDIP RESET (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (T0) PD4 VCC GND XTAL1 XTAL2 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP)
AT90S/LS4433 Description The AT90S4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S4433 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers.
Block Diagram Figure 1. The AT90S4433 Block Diagram PC0 - PC5 VCC PORTC DRIVERS GND DATA REGISTER PORTC DATA DIR. REG.
AT90S/LS4433 Pin Descriptions VCC Supply voltage. GND Ground. Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S4433 as listed on page 73.
Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which can be configured for use as an On-chip Oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used. External Clock If the Oscillator is to be used as a clock for an external device, the clock signal from XTAL2 may be routed to one HC buffer while reducing the load capacitor by 5 pF, as shown in Figure 3.
AT90S/LS4433 Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two-stage pipeline.
AT90S/LS4433 Figure 6. AT90S4433 Memory Maps Program Memory Data Memory $000 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (2K x 16) $005F $0060 Internal SRAM (128 x 8) $00DF $7FF A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory.
General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 0 Addr.
AT90S/LS4433 In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed.
The direct addressing reaches the entire data space. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data SRAM in the AT90S4433 are all accessible through all these addressing modes.
AT90S/LS4433 I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in six bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing Data Space 20 19 31 16 OP $0000 Rr/Rd 16 LSBs 15 0 $00DF A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 14.
Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 15 0 X, Y, OR Z - REGISTER $00DF Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Predecrement Figure 16. Data Indirect Addressing with Pre-decrement Data Space $0000 15 0 X, Y, OR Z - REGISTER -1 $00DF The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Data Indirect with Postincrement Figure 17.
AT90S/LS4433 Constant Addressing Using the LPM Instruction Figure 18. Code Memory Constant Addressing PROGRAM MEMORY $000 $7FF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 2K), the LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 19. Indirect Program Memory Addressing PROGRAM MEMORY $000 $7FF Program execution continues at address contained by the Z-register (i.e.
EEPROM Data Memory The AT90S4433 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The access between the EEPROM and the CPU is described on page 53, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register. For the SPI Data downloading, see page 93 for a detailed description.
AT90S/LS4433 Figure 23. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø Address Prev. Address Address Write Data WR Read Data RD I/O Memory The I/O space definition of the AT90S4433 is shown in Table 2. Table 2.
Table 2.
AT90S/LS4433 Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as: Bit 7 6 5 4 3 2 1 0 $3F ($5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
Stack Pointer – SP The AT90S4433 Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the AT90S4433 data memory has $0DF locations, eight bits are used. 7 6 5 4 3 2 1 0 $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SP The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located.
AT90S/LS4433 The most typical program setup for the Reset and Interrupt Vector addresses are: Address Labels Code Comments $000 rjmp RESET ; Reset Handler $001 rjmp EXT_INT0 ; IRQ0 Handler $002 rjmp EXT_INT1 ; IRQ1 Handler $003 rjmp TIM1_CAPT ; Timer1 Capture Handler $004 rjmp TIM1_COMP ; Timer1 compare Handler $005 rjmp TIM1_OVF ; Timer1 Overflow Handler $006 rjmp TIM0_OVF ; Timer0 Overflow Handler $007 rjmp SPI_STC; ; SPI Transfer Complete Handler $008 rjmp UART_RXC ;
Figure 24. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit BODEN BODLEVEL Brown-out Reset Circuit Internal Reset VCC Watchdog Timer CKSEL[2:0] On-chip RC Oscillator Counter Reset Reset Circuit RESET Delay Counters Full CK Table 4. Reset Characteristics (VCC = 5.0V) Symbol VPOT(1) Min Typ Max Units Power-on Reset Threshold Voltage, rising 1.0 1.4 1.8 V Power-on Reset Threshold Voltage, falling 0.4 0.6 0.
AT90S/LS4433 Table 5. Reset Delay Selections CKSEL [2:0] Start-up Time, tTOUT at VCC = 2.7V Start-up Time, tTOUT at VCC = 5.
Figure 25. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Controlled Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
AT90S/LS4433 Brown-out Detection AT90S4433 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during the operation. The power supply must be decoupled with a 47 nF to 100 nF capacitor if the BOD function is used. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases to a value below the trigger level, the Brown-out Reset is immediately activated.
MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 $34 ($54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
AT90S/LS4433 Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software.
• Bit 6 – INTF0: External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding Interrupt Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 in GIMSK is set (one), the MCU will jump to the Interrupt Vector. The flag is always cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured as level interrupt. • Bits 5.
AT90S/LS4433 Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 $38 ($58) TOV1 OCF1 – – ICF1 – TOV0 – Read/Write R/W R/W R R R/W R R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag.
External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR).
AT90S/LS4433 • Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 7. Table 7. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Any logical change on INT1 generates an interrupt request.
Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset.
AT90S/LS4433 Timer/Counters The AT90S4433 provides two general purpose Timer/Counters – one 8-bit T/C and one 16-bit T/C. Timer/Counters0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a Timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. Timer/Counter Prescaler Figure 30.
OCF1 OCIE1 Figure 31. Timer/Counter0 Block Diagram T0 Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 ($53) – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7 – 3 – Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero.
AT90S/LS4433 The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK Oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting.
Interrupt Flag Register (TIFR). The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
AT90S/LS4433 Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM11 COM10 – – – – PWM11 PWM10 Read/Write R/W R/W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 $2F ($4F) TCCR1A • Bits 7, 6 – COM11, COM10: Compare Output Mode1, Bits 1, and 0 The COM11 and COM10 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin actions affect pin OC1 (Output Compare pin 1).
Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 $2E ($4E) ICNC1 ICES1 – – CTC1 CS12 CS11 CS10 Read/Write R/W R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the Input Capture trigger Noise Canceler function is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the ICP (Input Capture Pin) as specified.
AT90S/LS4433 • Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1, and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 12. Clock 1 Prescale Select CS12 CS11 CS10 Description 0 0 0 Stop, the Timer/Counter1 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T1, falling edge 1 1 1 External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function.
the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
AT90S/LS4433 Timer/Counter1 Input Capture Register – ICR1H and ICR1L Bit 15 $27 ($47) 14 13 12 11 10 9 8 MSB ICR1H $26 ($46) LSB 7 Read/Write Initial Value 6 5 4 3 2 1 ICR1L 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Input Capture Register is a 16-bit, read only register.
Table 14. Compare1 Mode Select in PWM Mode COM11 COM10 Effect on OC1 0 0 Not connected 0 1 Not connected 1 0 Cleared on compare match, up-counting. Set on compare match, downcounting (non-inverted PWM). 1 1 Cleared on compare match, down-counting. Set on compare match, upcounting (inverted PWM). Note that in the PWM mode, the ten least significant OCR1 bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches TOP.
AT90S/LS4433 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 6. See characterization data for typical values at other VCC levels. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown inTable 16. Table 16. Watchdog Timer Prescale Select(1) WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 3.0V Typical Time-out at V CC = 5.
AT90S/LS4433 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. An ongoing EEPROM write operation will complete even if a reset condition occurs.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address.
AT90S/LS4433 Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S4433 and peripheral devices or between several AVR devices. The AT90S4433 SPI features include the following: • Full Duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode Figure 36.
AT90S/LS4433 Figure 37. SPI Master-slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in. Otherwise, the first byte is lost.
pins are inputs. When SS is driven high, externally all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost.
AT90S/LS4433 SPI Control Register – SPCR Bit 7 6 5 4 3 2 1 0 $0D ($2D) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the global interrupts are enabled. • Bit 6 – SPE: SPI Enable When the SPE bit is set (one), the SPI is enabled.
SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 $0E ($2E) SPIF WCOL – – – – – 0 – Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
AT90S/LS4433 UART The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART).
data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control and Status Register B, UCSRB is set), the TXB8 bit in UCSRB is transferred to bit nine in the Transmit Shift Register. On the baud rate clock following the transfer operation to the Shift Register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first.
AT90S/LS4433 The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the RXD pin at samples 8, 9, and 10.
Multi-processor Communication Mode The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data bytes as normal, while the other slave MCUs will ignore the data bytes until another address byte is received.
AT90S/LS4433 UART Control UART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 $0C ($2C) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 UDR The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read.
• Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. • Bit 3 – OR: OverRun This bit is set if an OverRun condition is detected, i.e., when a character already present in the UDR Register is not read before the next character has been shifted into the Receiver Shift Register.
AT90S/LS4433 • Bit 3 – TXEN: Transmitter Enable This bit enables the UART Transmitter when set (one). When disabling the Transmitter while transmitting a character, the Transmitter is not disabled before the character in the Shift Register plus any following character in UDR has been completely transmitted. • Bit 2 – CHR9: 9-bit Characters When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits.
Table 19. UBR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBR= 25 0.2 UBR= 47 0.0 UBR= 51 0.2 UBR= 63 0.0 4800 UBR= 12 0.2 UBR= 23 0.0 UBR= 25 0.2 UBR= 31 0.0 6 7.5 UBR= 9600 UBR= 11 0.0 UBR= 12 0.2 UBR= 15 0.0 UBR= 3 7.8 UBR= UBR= 8 3.7 UBR= 10 3.1 14400 7 0.0 2 7.8 UBR= 6 7.5 UBR= 19200 UBR= 5 0.0 UBR= 7 0.0 1 7.8 UBR= 3 7.8 UBR= 4 6.3 28800 UBR= 3 0.0 UBR= 1 22.9 UBR= 2 7.8 UBR= 38400 UBR= 2 0.0 UBR= 3 0.0 0 7.8 UBR= 1 7.
AT90S/LS4433 UART Baud Rate Register – UBRR Bit 15 14 13 12 11 $03 ($23) – – – – MSB $09 ($29) MSB 7 Read/Write Initial Value 6 5 4 3 10 2 9 1 8 LSB UBRRHI LSB UBRR 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This is a 12-bit register that contains the UART Baud Rate according to the equation on the previous page.
Analog Comparator The Analog Comparator compares the input values on the positive input PD6 (AIN0) and negative input PD7 (AIN1). When the voltage on the positive input PD6 (AIN0) is higher than the voltage on the negative input PD7 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
AT90S/LS4433 • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical “1” to the flag.
Analog-to-Digital Converter Features • • • • • • • • • • 10-bit Resolution ±2 LSB Absolute Accuracy 0.5 LSB Integral Non-linearity 65 - 260 µs Conversion Time Up to 15 kSPS Six Multiplexed Input Channels Rail-to-Rail Input Range Free Run or Single Conversion Mode Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The AT90S4433 features a 10-bit successive approximation ADC.
AT90S/LS4433 Operation The ADC can operate in two modes: Single Conversion and Free Run mode. In Single Conversion mode, each conversion will have to be initiated by the user. In Free Run mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADMUX Register selects which one of the six analog input channels is to be used as input to the ADC. The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR.
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of the conversion. The result is ready and written to the ADC Result Register after 13 cycles.
AT90S/LS4433 Figure 47. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion complete MUX and REFS Update MUX and REFS Update Figure 48.
ADC Multiplexer Select Register – ADMUX Bit 7 6 5 4 3 2 1 0 $07 ($27) – ADCBG – – – MUX2 MUX1 MUX0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S4433, and should be written to zero if accessed. • Bit 6 – ADCBG: ADC Bandgap Select When this bit is set and the BOD is enabled (BODEN Fuse is programmed), a fixed bandgap voltage of 1.22V ± 0.1V replaces the normal input to the ADC.
AT90S/LS4433 • Bit 5 – ADFR: ADC Free Run Select When this bit is set (one), the ADC operates in Free Run mode. In this mode, the ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free Run mode. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the Ibit in SREG are set (one).
Scanning Multiple Channels Since change of analog channel always is delayed until a conversion is finished, the Free Run mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the channel shift. However, the user should take the following fact into consideration: The interrupt triggers once the result is ready to be read. In Free Run mode, the next conversion will start immediately when the interrupt triggers.
AT90S/LS4433 ADC Characteristics TA = -40°C to 85°C Symbol Parameter Condition Min Typ Resolution Bits Absolute Accuracy VREF = 4V ADC clock = 200 kHz 1 Absolute Accuracy VREF = 4V ADC clock = 1 MHz 4 LSB Absolute Accuracy VREF = 4V ADC clock = 2 MHz 16 LSB Integral Non-linearity VREF > 2V 0.5 LSB Differential Non-linearity VREF > 2V 0.
I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B Port B is a 6-bit bi-directional I/O port.
AT90S/LS4433 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All six pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin.
controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. See the description of the SPI port for further details. • OC1 – Port B, Bit 1 OC1, Output Compare Match output: PB1 pin can serve as an external output for the Timer/Counter1 Output Compare. The pin has to be configured as an output (DDB1 set [one]) to serve this function. See the timer description on how to enable this function.
AT90S/LS4433 Figure 51. Port B Schematic Diagram (Pin PB1) DDB1 PB1 PORTB1 WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB Figure 52.
Figure 53. Port B Schematic Diagram (Pin PB3) RD MOS PULLUP RESET Q R D DDB3 WD RESET R Q D PORTB3 PB3 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI MASTER OUT SPI SLAVE IN Figure 54.
AT90S/LS4433 Figure 55. Port B Schematic Diagram (Pin PB5) RD MOS PULLUP RESET Q R D DDB5 WD RESET R Q D PORTB5 PB5 DATA BUS C C RL WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI CLOCK OUT SPI CLOCK IN Port C Port C is a 6-bit bi-directional I/O port.
Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 $15 ($35) – – PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $14 ($34) – – DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $13 ($33) – – PINC5 PINC4
AT90S/LS4433 Port C Schematics Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 56.
Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31), and the Port D Input Pins – PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA.
AT90S/LS4433 Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be cleared (zero) or the pin has to be configured as an output pin.
• TXD – Port D, Bit 1 Transmit Data (Data Output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1. • RXD – Port D, Bit 0 Receive Data (Data Input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regardless of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized.
AT90S/LS4433 Figure 58. Port D Schematic Diagram (Pin PD1) RD MOS PULLUP RESET Q R D DDD1 C DATA BUS WD RESET R Q D PORTD1 PD1 C RL WP RP WP: WD: RL: RP: RD: TXD: TXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN TXD Figure 59.
Figure 60. Port D Schematic Diagram (Pins PD4 and PD5) DDDn PDn PORTBn WP: WD: RL: RP: RD: n: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5 2 Figure 61.
AT90S/LS4433 Memory Programming Program and Data Memory Lock Bits The AT90S4433 MCU provides two Lock bits, which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28. The Lock bits can only be erased with the Chip Erase command. Table 28. Lock Bit Protection Modes Memory Lock Bits Mode LB1 LB2 1 1 1 No memory lock features enabled. 2 0 1 Further programming of the Flash and EEPROM is disabled.
Programming the Flash and EEPROM Atmel’s AT90S4433 offers 4K bytes of In-System Reprogrammable Flash Program memory and 256 bytes of EEPROM Data memory. The AT90S4433 is shipped with the On-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a High-voltage (12V) Parallel Programming mode and a Low-voltage Serial Programming mode.
AT90S/LS4433 Table 30. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command OE PD2 I Output Enable (active low) WR PD3 I Write Pulse (active low) BS PD4 I Byte Select (“0” selects Low Byte, “1” selects High Byte) XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 DATA PC1 - 0, PB5 - 0 I/O Bi-directional Data Bus (output when OE is low) Table 31.
Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash or EEPROM is reprogrammed. A: Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5.
AT90S/LS4433 G: Write Data High Byte 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 64 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: • The command needs to be loaded only once when writing or reading multiple memory locations.
Figure 64. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” for details on command and address loading): A: Load Command “0000 0010”. B: Load Address High Byte ($00 - $07). C: Load Address Low Byte ($00 - $FF). 1. Set OE to “0”, and BS to “0”. The Flash word Low Byte can now be read at DATA. 2. Set BS to “1”.
AT90S/LS4433 Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming the Flash” for details on command and data loading): A: Load Command “0100 0000”. B: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit Bits 7 - 6 = “1”. These bits are reserved and should be left unprogrammed (“1”). 1.
Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” for details on command and address loading): A: Load Command “0000 1000”. B: Load Address Low Byte ($00 - $02). 1. Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA. 2. Set OE to “1”. Parallel Programming Characteristics Figure 65.
AT90S/LS4433 Serial Downloading Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output) (see Figure 66). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. Figure 66. Serial Programming and Verify AT90S/LS4433 4.0 - 6.0 V (AT90S4433) 2.7 - 6.0 V (AT90LS4433) VCC DATA OUT INSTR.
ing the third byte of the Programming Enable instruction. Whether or not the echo is correct, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2.
AT90S/LS4433 Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte.
Table 35. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming while RESET is low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash and EEPROM memory arrays. 0010 H000 xxxx xaaa bbbb bbbb oooo oooo Read H (high or low) data o from program memory at word address a:b. 0100 H000 xxxx xaaa bbbb bbbb iiii iiii Write H (high or low) data i to program memory at word address a:b.
AT90S/LS4433 Serial Programming Characteristics Figure 68. Serial Programming Timing MOSI tOVSH SCK tSLSH tSHOX tSHSL MISO tSLIV Table 36. Serial Programming Characteristics, TA = -40°C to 85°C, V CC = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Min 1/tCLCL Oscillator Frequency (VCC = 2.7 - 6.0V) tCLCL Oscillator Period (VCC = 2.7 - 6.0V) 1/tCLCL Oscillator Frequency (VCC = 4.0 - 6.0V) tCLCL Oscillator Period (VCC = 4.0 - 6.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
AT90S/LS4433 DC Characteristics (Continued) TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5.0V Vin = VCC/2 IACLK Analog Comparator Input Leakage A VCC = 5.0V Vin = VCC /2 tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min Typ -50.0 750.0 500.0 Max Units 40.0 mV 50.0 nA ns 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”). 2.
External Clock Drive Waveforms Figure 69. External Clock VIH1 VIL1 Table 39. External Clock Drive VCC = 2.7V to 6.0V 100 VCC = 4.0V to 6.0V Symbol Parameter Min Max Min Max Units 1/tCLCL Oscillator Frequency 0.0 4.0 0.0 8.0 MHz tCLCL Clock Period 250.0 125.0 ns tCHCX High Time 100.0 50.0 ns tCLCX Low Time 100.0 50.0 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.
AT90S/LS4433 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 71. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. VCC FREQUENCY = 4 MHz 14 12 TA = 25˚C TA = 85˚C ICC (mA) 10 8 6 4 2 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 72. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA = 25˚C 18 VCC = 6V ICC (mA) 16 14 VCC = 5.5V 12 VCC = 5V 10 VCC = 4.5V 8 VCC = 4V 6 VCC = 3.6V VCC = 3.3V VCC = 3.0V 4 VCC = 2.
AT90S/LS4433 Figure 73. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. VCC FREQUENCY = 4 MHz 6 5 TA = 85˚C ICC (mA) 4 TA = 25˚C 3 2 1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 74. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 25 TA = 85˚C 20 ICC (µA) 15 TA = 70˚C 10 5 TA = 45˚C TA = 25˚C 0 2 2.5 3 3.5 4 4.5 5 5.
Figure 75. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 120 100 ICC (µA) 80 TA = 85˚C TA = 25˚C 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 76. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC BROWN-OUT DETECTOR ENABLED 140 120 TA = 85˚C ICC (µA) 100 TA = 25˚C 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.
AT90S/LS4433 Figure 77. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 0.9 0.8 0.7 TA = 25˚C 0.6 ICC (mA) TA = 85˚C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Analog Comparator offset voltage is measured as absolute offset. Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.
Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 80. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 IACLK (nA) 40 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
AT90S/LS4433 Figure 81. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1600 TA = 25˚C 1400 TA = 85˚C 1200 FRC (kHz) 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 82. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 120 TA = 25˚C 100 TA = 85˚C IOP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.
Figure 83. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 30 TA = 25˚C 25 TA = 85˚C IOP (µA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 84. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 80 70 TA = 25˚C 60 IOL (mA) 50 40 TA = 85˚C 30 20 10 0 0 0.5 1 1.5 2 2.
AT90S/LS4433 Figure 85. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 18 TA = 25˚C 16 14 TA = 85˚C IOH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Figure 86. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 30 TA = 25˚C 25 IOL (mA) 20 TA = 85˚C 15 10 5 0 0 0.5 1 1.
Figure 87. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 6 TA = 25˚C 5 IOH (mA) 4 TA = 85˚C 3 2 1 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 88. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.
AT90S/LS4433 Figure 89. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC TA = 25˚C 0.18 0.16 Input Hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page page 19 $3F ($5F) SREG I T H S V N Z C $3E ($5E) Reserved – – – – – – – – page 20 $3D ($5D) SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 20 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 INT0 – – – – – – page 27 $3A ($5A) GIFR INTF1 INTF0 $39 ($59) TIMSK TOIE1 OCIE1 – – TICIE1 – TOIE0 – page 28 $38 ($58) TIFR TOV1 OCF1 – – ICF1 – TOV0 – page 29 $37 ($57) R
AT90S/LS4433 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers
AT90S/LS4433 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags LD Rd, Y Load Indirect Rd ← (Y) None LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-inc. Rd ← (Z), Z ← Z + 1 None 2 LD Rd, -Z Load Indirect and Pre-dec.
Ordering Information Power Supply Speed (MHz) 2.7 - 6.0V 4 4.0 - 6.0V 8 Ordering Code Package Operation Range AT90LS4433-4AC AT90LS4433-4PC 32A 28P3 Commercial (0°C to 70°C) AT90LS4433-4AI AT90LS4433-4PI 32A 28P3 Industrial (-40°C to 85°C) AT90S4433-8AC AT90S4433-8PC 32A 28P3 Commercial (0°C to 70°C) AT90S4433-8AI AT90S4433-8PI 32A 28P3 Industrial (-40°C to 85°C) Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.
AT90S/LS4433 Packaging Information 32A 32-lead, Thin (1.0mm) Plastic Quad Flatpack (TQFP), 7x7mm body, 2.0mm footprint, 0.8mm pitch. Dimensions in Millimeters and (Inches)* JEDEC STADARD MS-026 ABA 9.25 (0.364) 8.75 (0.344) PIN 1 ID 0.45 (0.018) 0.30 (0.012) PIN 1 9.25 (0.364) 8.75 (0.344) 0.80 (0.0315) BSC 7.10 (0.280) 6.90 (0.272) SQ 1.20 (0.047) MAX 0.20 (0.008) 0.09 (0.004) 0º~7º 0.75 (0.030) 0.45 (0.018) 0.15 (0.006) 0.05 (0.
28P3 28-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide, (0.288" body width) Dimensions in Millimeters and (Inches)* 34.80(1.370) 34.54(1.360) 7.49(0.295) 7.11(0.280) 4.57(0.180)MAX 3.56(0.140) 3.05(0.120) 0.56(0.022) 2.54(0.100)BSC 1.65(0.065) 0.38(0.015) 1.27(0.050) 8.26(0.325) 7.62(0.300) 0º~ 15º REF 0.38(0.015) 10.20(0.400)MAX *Controlling dimension: Inches REV.
AT90S/LS4433 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F • • • • • • Fuses and Programming Mode Incorrect Channel Change in Free Running Mode Bandgap Reference Stabilizing Time Brown-out Detection Level Serial Programming at Voltages below 2.9V UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled 6. Fuses and Programming Mode After programming the Fuses in Serial Programming mode, it is not possible to program the Flash or EEPROM.
1. UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled The UART will detect a UART start bit and start reception even if the UART is not enabled. If this occurs, the first byte after reenabling the UART will be corrupted. Problem Fix/Workaround Make sure that the RX line is high at start-up and when the UART is disabled. An external RS-232 level converter keeps the line high during start-up.
AT90S/LS4433 Data Sheet Change Log for AT90S/LS4433 This section containes a log on the changes made to the data sheet for AT90S/LS4433. All refereces to pages in Change Log, are referred to this document. Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 1 Updated minimum AREF Voltage on page 5 and page 64. 2 Corrected VBOT Max for BODLEVEL = 1 in Table 4 on page 22. 3 Updated Corporate Template. 1 Added wathermark “Not recommended for new designs. Use ATmega8”.
AT90S/LS4433 1042G–AVR–09/02
AT90S/LS4433 Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Description ............................................................................................ 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.............................
Prescaling ........................................................................................................... ADC Noise Canceler Function ............................................................................ Scanning Multiple Channels ............................................................................... ADC Noise Canceling Techniques ..................................................................... ADC Characteristics TA = -40°C to 85°C .........................................
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