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AT90S/LS8535

1041H–11/01

TEMP, interrupts must be disabled during access from the main program (and from

interrupt routines if interrupts are allowed from within interrupt routines).

• TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the written data is placed in the

TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is

combined with the byte data in the TEMP register, and all 16 bits are written to the

TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte

TCNT1H must be accessed first for a full 16-bit register write operation.

• TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent

to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.

When the CPU reads the data in the high byte TCNT1H, the CPU receives the data

in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for

a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-

ten value.

Timer/Counter1 Output

Compare Register – OCR1AH

AND OCR1AL

Timer/Counter1 Output

Compare Register – OCR1BH

AND OCR1BL

The output compare registers are 16-bit read/write registers.

The Timer/Counter1 Output Compare registers contain the data to be continuously com-

pared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status registers. A compare match only occurs if

Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A

or OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the

compare event.

Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem-

porary register (TEMP) is used when OCR1A/B are written to ensure that both bytes are

updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the

data is temporarily stored in the TEMP register. When the CPU writes the low byte,

Bit 151413121110 9 8

$2B ($4B) MSB OCR1AH

$2A ($4A) LSB OCR1AL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000