Manual

58
AT90S/LS8535
1041H–11/01
• Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the oscillator
clock frequency f
cl
is shown in Table 23.
SPI Status Register – SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS
is an input and
is driven low when the SPI is in Master Mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one) and then accessing the SPI Data Register.
• Bit 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
The SPI interface on the AT90S8535 is also used for program memory and EEPROM
downloading or uploading. See page 99 for serial programming and verification.
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the regis-
ter file and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Table 23. Relationship between SCK and the Oscillator Frequency
SPR1 SPR0 SCK Frequency
00 f
cl
/4
01 f
cl
/16
10 f
cl
/64
11 f
cl
/128
Bit 76543210
$0E ($2E) SPIF WCOL ––––––SPSR
Read/WriteRRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
$0F ($2F) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X Undefined