Manual

67
AT90S/LS8535
1041H–11/01
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly
connected to the Input Capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
cleared (zero), no connection between the Analog Comparator and the Input Capture
function is given. To make the comparator trigger the Timer/Counter1 Input Capture
interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the Analog Comparator interrupt.
The different settings are shown in Table 25.
Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis-
abled by clearing its interrupt enable bit in the ACSR register. Otherwise an interrupt can
occur when the bits are changed.
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a “1” back into ACI if it is read as set, thus clearing the flag.
Table 25. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle
01Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge