83
AT90S/LS8535
1041H–11/01
Figure 57. Port B Schematic Diagram (Pin PB7)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB7
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB7
PORTB7
SPE
MSTR
SPI CLOCK
OUT
SPI CLOCK
IN
RL
RP
