Manual

89
AT90S/LS8535
1041H–11/01
Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 61. Port D Schematic Diagram (Pin PD0)
Figure 62. Port D Schematic Diagram (Pin PD1)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD0
RXD
RXEN
WP:
WD:
RL:
RP:
RD:
RXD:
RXEN:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART RECEIVE DATA
UART RECEIVE ENABLE
DDD0
PORTD0
RL
RP
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
RP
RL
MOS
PULL-
UP
PD1
R
R
WP:
WD:
RL:
RP:
RD:
TXD:
TXEN:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART TRANSMIT DATA
UART TRANSMIT ENABLE
DDD1
PORTD1
TXEN
TXD