Manual

91
AT90S/LS8535
1041H–11/01
Figure 65. Port D Schematic Diagram (Pin PD6)
Figure 66. Port D Schematic Diagram (Pin PD7)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD6
R
R
WP:
WD:
RL:
RP:
RD:
ACIC:
ACO:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
COMPARATOR IC ENABLE
COMPARATOR OUTPUT
DDD6
PORTD6
NOISE CANCELER EDGE SELECT ICF1
ICNC1 ICES1
0
1
ACIC
ACO
RL
RP