Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 89 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 12 MIPS Throughput at 12 MHz Data and Non-volatile Program Memory – 1K Byte of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 64 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPRO
Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working registers.
AT90S1200 ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or hardware Reset. The device is manufactured using Atmel’s high-density nonvolatile memory technology.
Figure 2. Oscillator Connections MAX 1 HC BUFFER HC C2 C1 XTAL2 XTAL1 GND Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. Figure 3. External Clock Drive Configuration On-chip RC Oscillator 4 An On-chip RC Oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. If enabled, the AT90S1200 can operate with no external components.
AT90S1200 Architectural Overview The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. Figure 4.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subroutines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
AT90S1200 Program and Data Addressing Modes The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Register Direct, Single Register Rd Figure 6. Direct Single Register Addressing The operand is contained in register d (Rd).
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 9. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Relative Program Addressing, RJMP and RCALL Figure 10. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
AT90S1200 EEPROM Data Memory The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 25 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register. For the SPI data downloading, see page 44 for a detailed description.
I/O Memory The I/O space definition of the AT90S1200 is shown in the following table. Table 1.
AT90S1200 Status Register – SREG The AVR status register (SREG) at I/O space location $3F is defined as: Bit 7 6 5 4 3 2 1 0 $3F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
Reset and Interrupt Handling The AT90S1200 provides three different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors.
AT90S1200 Figure 13. Reset Logic Power-on Reset Circuit VCC POR Reset Circuit S Q R Q Counter Reset RESET Watchdog Timer On-chip RC Oscillator Time-out 14-stage Ripple Counter Internal Reset 100 - 500K Table 3. Reset Characteristics (VCC = 5.0V) Symbol VPOT(1) Min Typ Max Units Power-on Reset Threshold Voltage (rising) 0.8 1.2 1.6 V Power-on Reset Threshold Voltage (falling) 0.2 0.4 0.6 V VRST Pin Threshold Voltage – – 0.85 VCC V tPOR Power-on Reset Period 2.0 3.0 4.
been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a timing example on this. Figure 15. MCU Start-up, RESET Controlled Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
AT90S1200 Figure 17. Watchdog Reset during Operation Interrupt Handling The AT90S1200 has two Interrupt Mask Control Registers: the GIMSK (General Interrupt Mask Register) at I/O space address $3B and the TIMSK (Timer/Counter Interrupt Mask Register) at I/O address $39. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts.
• Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0 can be activated even if the pin is configured as an output. See also page 17. • Bits 5..
AT90S1200 External Interrupts The External Interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or low level. This is set up as described in the specification for the MCU Control Register (MCUCR). When INT0 is level triggered, the interrupt is pending as long as INT0 is held low. The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt. The interrupt flag can not be directly accessed by the user.
MCU Control Register – MCUCR The MCU Control Register contains general microcontroller control bits for general MCU control functions. Bit 7 6 5 4 3 2 1 0 $35 – – SE SM – – ISC01 ISC00 Read/Write R R R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero.
AT90S1200 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Timer/Counter0 Th e A T90 S 12 00 pr o v id e s o ne ge ne r al pu r p os e 8 - bi t Ti m er / Co un te r . Th e Timer/Counter0 gets the prescaled clock from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a Timer with an internal clock time base or as a Counter with an external pin connection, which triggers the counting. Timer/Counter0 Prescaler Figure 18 shows the general Timer/Counter0 prescaler. Figure 18.
AT90S1200 Figure 19. Timer/Counter0 Block Diagram T0 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter0 Control Register (TCCR0).
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 5. Clock 0 Prescale Select CS02 CS01 CS00 Description 0 0 0 Stop, the Timer/Counter0 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T0, falling edge 1 1 1 External Pin T0, rising edge The Stop condition provides a Timer Enable/Disable function.
AT90S1200 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted, see Table 6 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer.
Table 6. Watchdog Timer Prescale Select Number of WDT Oscillator Cycles Typical Time-out at VCC = 3.0V Typical Time-out at VCC = 5.0V 0 16K cycles 47 ms 15 ms 0 1 32K cycles 94 ms 30 ms 0 1 0 64K cycles 0.19 s 60 ms 0 1 1 128K cycles 0.38 s 0.12 s 1 0 0 256K cycles 0.75 s 0,24 s 1 0 1 512K cycles 1.5 s 0.49 s 1 1 0 1,024K cycles 3.0 s 0.97 s 1 1 1 2,048K cycles 6.0 s 1.
AT90S1200 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Powerup/down.
• Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5 ms at VCC = 5V and 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte.
AT90S1200 Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) and the negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output (ACO) is set (one). The comparator’s output can be set to trigger the Analog Comparator interrupt. The user can select interrupt triggering on comparator output rise, fall or toggle.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator Interrupt.
AT90S1200 I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B Port B is an 8-bit bi-directional I/O port.
Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) and the pin is configured as an input pin, the MOS pull-up resistor is activated.
AT90S1200 Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 22.
Figure 23. Port B Schematic Diagram (Pins PB2, PB3, and PB4) 2, Figure 24.
AT90S1200 Figure 25. Port B Schematic Diagram (Pin PB6) Figure 26.
Port D Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD ($12), Data Direction Register – DDRD ($11), and the Port D Input Pins – PIND ($10). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.
AT90S1200 Table 11. DDDn Bits’ Effect on Port D Pins DDDn PORTDn I/O Pull-up 0 0 Input No Tri-state (High-Z) 0 1 Input Yes PDn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output Note: Alternate Functions for Port D Comment n: 6…0, pin number. The alternate functions of Port D are: • T0 – Port D, Bit 4 T0, Timer/Counter0 clock source. See the timer description for further details.
Figure 28. Port D Schematic Diagram (Pin PD2) Figure 29.
AT90S1200 Memory Programming Program and Data Memory Lock Bits The AT90S1200 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 12. The Lock bits can only be erased with the Chip Erase command. Table 12. Lock Bit Protection Modes Memory Lock Bits Mode LB1 LB2 1 1 1 No memory lock features enabled. 2 0 1 Further programming of the Flash and EEPROM is disabled.
the self-timed write instruction in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 13. Table 13. Supply Voltage during Programming Parallel Programming Part Serial Programming Parallel Programming AT90S1200 2.7 - 6.0V 4.5 - 5.5V This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S1200. Figure 30.
AT90S1200 . Table 15. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte for Flash determined by BS). 0 1 Load Data (High or low data byte for Flash determined by BS). 1 0 Load Command 1 1 No Action, Idle Table 16.
4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $01). 4. Give XTAL1 a positive pulse. This loads the address high byte. C: Load Address Low Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “0”. This selects low byte. 3. Set DATA = Address low byte ($00 - $FF). 4. Give XTAL1 a positive pulse.
AT90S1200 Figure 31. Programming the Flash Waveforms DATA $10 ADDR. HIGH ADDR.LOW DATA LOW XA1 XA0 BS XTAL1 WR RDY/BSY RESET 12V OE Figure 32. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” for details on command and address loading): 1. A: Load Command “0000 0010”. 2. B: Load Address High Byte ($00 - $01). 3.
Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. C: Load Address Low Byte ($00 - $3F). 3. D: Load Data Low Byte ($00 - $FF). 4. E: Write Data Low Byte. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” for details on command and address loading): 1. A: Load Command “0000 0011”. 2.
AT90S1200 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” on page 39 for details on command and address loading): 1. A: Load Command “0000 1000”. 2. C: Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA. Set OE to “1”. Parallel Programming Characteristics Figure 33.
Serial Downloading Both the program and data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output) (see Figure 34). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. Figure 34. Serial Programming and Verify 2.7 - 6.
AT90S1200 3. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 21 on page 47 for tWD_ERASE value. 4. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Wait tWD_PROG after transmitting the instruction.
Figure 35. Serial Programming Waveforms Table 19. Serial Programming Instruction Set for AT90S1200 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable serial programming while RESET is low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase both Flash and EEPROM memory arrays.
AT90S1200 Serial Programming Characteristics Figure 36. Serial Programming Timing MOSI tOVSH SCK tSLSH tSHOX tSHSL MISO tSLIV Table 20. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Min 1/tCLCL Oscillator Frequency (VCC = 2.7 - 4.0V) tCLCL Oscillator Period (VCC = 2.7 - 4.0V) 1/tCLCL Oscillator Frequency (VCC = 4.0 - 6.0V) tCLCL Oscillator Period (VCC = 4.0 - 6.0V) tSHSL Typ 0 Max Units 4.0 MHz 250.0 ns 0 12.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
AT90S1200 DC Characteristics TA = -40×C to 85×C, VCC = 2.7V to 6.0V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/ 2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/ 2 tACPD Notes: 1. 2. 3. 4. 5. Min -50.0 Typ Max Units 40.0 mV 50.0 nA 750.0 ns Analog Comparator VCC = 2.7V 500.0 Propagation Delay VCC = 4.0V “Max” means the highest value where the pin is guaranteed to be read as low.
External Clock Drive Waveforms Figure 37. External Clock Drive VIH1 VIL1 External Clock Drive Table 23. External Clock Drive VCC = 2.7V to 4.0V 50 VCC = 4.0V to 6.0V Min Max Min Max Units 0 4.0 0 12.0 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 250.0 83.3 ns tCHCX High Time 100.0 33.3 ns tCLCX Low Time 100.0 33.3 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.
AT90S1200 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 39. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 10 TA = -40˚C 9 TA = 25˚C 8 7 I cc(mA) TA = 85˚C 6 5 4 3 2 1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 40. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 7 6 TA = 25˚C 5 I cc(mA) TA = 85˚C 4 3 2 1 0 2 2.5 3 3.5 4 4.5 5 5.
AT90S1200 Figure 41. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA= 25˚C 4.5 Vcc= 6V 4 3.5 Vcc= 5.5V I cc(mA) 3 Vcc= 5V 2.5 Vcc= 4.5V 2 Vcc= 4V Vcc= 3.6V Vcc= 3.3V Vcc= 3.0V 1.5 1 Vcc= 2.7V 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency (MHz) Figure 42. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 2.5 TA = -40˚C TA = 25˚C 2 I cc(mA) 1.5 TA = 85˚C 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.
Figure 43. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 0.4 TA = 25˚C 0.35 0.3 TA = 85˚C I cc(mA) 0.25 0.2 0.15 0.1 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 44. Power-down Supply Current vs. VCC, Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 1.8 TA = 85˚C 1.6 I cc(µΑ) 1.4 1.2 1 TA = 70˚C 0.8 0.6 0.4 TA = 45˚C 0.2 TA = 25˚C 0 2 2.5 3 3.5 4 4.5 5 5.
AT90S1200 Figure 45. Power-down Supply Current vs. VCC, Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 140 TA = 25˚C 120 TA = 85˚C I cc(µΑ) 100 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 46. Internal RC Oscillator Frequency vs. VCC INTERNAL RC OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25˚C 1400 TA = 85˚C F RC (KHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.
Figure 47. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 1.2 1 TA = -40˚C TA = 25˚C I cc(mA) 0.8 0.6 TA = 85˚C 0.4 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Note: Analog comparator offset voltage is measured as absolute offset. Figure 48. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
AT90S1200 Figure 49. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 50. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 51. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 52. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.
AT90S1200 Figure 53. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 54. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 55. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 1.5 2 VOL (V) Figure 56. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.
AT90S1200 Note: Input threshold is measured at the center point of the hysteresis. Figure 57. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 Vcc Figure 58. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
AT90S1200 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F SREG I T H S V N Z C page 11 - INT0 - - - - - - page 15 Notes: 62 $3E Reserved $3D Reserved $3C Reserved $3B GIMSK $3A Reserved $39 TIMSK - - - - - - TOIE0 - page 16 $38 TIFR - - - - - - TOV0 - page 16 $37 Reserved $36 Reserved - - SE SM - - ISC01 ISC00 page 18 - - - - - CS02 CS01 CS00 $35 MCUCR $34 Reserved $33 TCCR0 $32
AT90S1200 Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers SUB Rd, Rr Subtract Two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry Two Registers SBCI Rd, K Subtract with Carry Constant from Reg.
Instruction Set Summary (Continued) Mnemonic Operands Description BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register CBI P, b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left through Carry ROR Rd Rotate Right through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit Load from T to Register SEC Set Carry CLC Clear Carry SEN Set Negative Flag CLN Clear N
AT90S1200 Ordering Information(1) Speed (MHz) Power Supply Ordering Code Package 4 2.7 - 6.0V AT90S1200-4PC AT90S1200-4SC AT90S1200-4YC 20P3 20S 20Y Commercial (0°C to 70°C) AT90S1200-4PI AT90S1200-4SI AT90S1200-4YI 20P3 20S 20Y Industrial (-40°C to 85°C) AT90S1200-12PC AT90S1200-12SC AT90S1200-12YC 20P3 20S 20Y Commercial (0°C to 70°C) AT90S1200-12PI AT90S1200-12SI AT90S1200-12YI 20P3 20S 20Y Industrial (-40°C to 85°C) 12 Note: 4.0 - 6.0V Operation Range 1.
Packaging Information 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.984 – E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.
AT90S1200 20S 20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 0.51(0.020) 0.33(0.013) 7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 2.65 (0.1043) 2.35 (0.0926) 0.30(0.0118) 0.10 (0.0040) 0.32 (0.0125) 0.23 (0.0091) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches REV.
20Y 20Y, 20-lead Plastic Shrink Small Outline (SSOP), 5.3mm body Width. Dimensions in Millimeters and (inches)* 0.38 (0.015) 0.25 (0.010) 5.38 (0.212) 7.90 (0.311) 5.20 (0.205) 7.65 (0.301) PIN 1 ID PIN 1 0.65 (0.0256) BSC 7.33 (0.289) 7.07 (0.278) 1.99 (0.078) 1.73 (0.068) 0.21 (0.008) 0.05 (0.002) 0.20 (0.008) 0.09 (0.004) 0º ~ 8º 0.95 (0.037) 0.63 (0.025) *Controlling dimension: millimeters REV.
AT90S1200 Table of Contents Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................................... Pin Descriptions.................................
Electrical Characteristics................................................................... 48 Absolute Maximum Ratings*............................................................................... DC Characteristics.............................................................................................. External Clock Drive Waveforms ........................................................................ External Clock Drive ........................................................................
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