Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz Data and Non-volatile Program Memory – 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of SRAM – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Fl
Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers.
AT90S2313 selectable power-saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next external interrupt or Hardware Reset. The device is manufactured using Atmel’s high-density non-volatile memory technology.
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3. Figure 2.
AT90S2313 Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Figure 4.
The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the Register File, $20 - $5F. The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is accessed with a 2-stage pipeline.
AT90S2313 General Purpose Register File Figure 6 shows the structure of the 32 general purpose registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers 7 0 Addr.
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed.
AT90S2313 SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized. Figure 8. SRAM Organization Register File Data Address Space R0 $00 R1 $01 R2 $02 … … R29 $1D R30 $1E R31 $1F I/O Registers $00 $20 $01 $21 $02 $22 … … $3D $5D $3E $5E $3F $5F Internal SRAM $60 $61 $62 … $DD $DE $DF The 224 data memory locations address the Register File, I/O memory and the data SRAM.
Program and Data Addressing Modes The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Register Direct, Single Register Rd Figure 9.
AT90S2313 Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 12. Direct Data Addressing A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 13. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word.
Data Indirect with Predecrement Figure 15. Data Indirect Addressing with Pre-decrement The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register. Data Indirect with Postincrement Figure 16. Data Indirect Addressing with Post-increment The X-, Y-, or Z-register is incremented after the operation. Operand address is the contents of the X-, Y-, or Z-register prior to incrementing.
AT90S2313 Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Memory Access and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
AT90S2313 Figure 22. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø Address Prev. Address Address Write Data WR Read Data RD I/O Memory The I/O space definition of the AT90S2313 is shown in Table 1. Table 1.
Table 1. AT90S2313 I/O Space(1) (Continued) Address Hex Name Function $12 ($32) PORTD Data Register, Port D $11 ($31) DDRD Data Direction Register, Port D $10 ($30) PIND Input Pins, Port D $0C ($2C) UDR UART I/O Data Register $0B ($2B) USR UART Status Register $0A ($2A) UCR UART Control Register $09 ($29) UBRR UART Baud Rate Register $08 ($28) ACSR Analog Comparator Control and Status Register Note: 1. Reserved and unused locations are not shown in the table.
AT90S2313 • Bit 5 – H: Half-carry Flag The Half-carry Flag H indicates a Half-carry in some arithmetic operations. See the Instruction Set description for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set description for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics.
Reset and Interrupt Handling The AT90S2313 provides 10 different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are automatically defined as the Reset and Interrupt Vectors.
AT90S2313 Reset Sources The AT90S2313 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. During Reset, all I/O Registers are then set to their initial values, and the program starts execution from address $000.
Table 4. Number of Watchdog Oscillator Cycles Power-on Reset FSTRT Time-out at VCC = 5V Number of WDT Cycles Programmed 0.28 ms 256 Unprogrammed 16.0 ms 16K A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. As shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer prevents the MCU from starting until after a certain period after VCC has reached the Power-on Threshold voltage (VPOT) (see Figure 24).
AT90S2313 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST ) on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired. Figure 26.
interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
AT90S2313 General Interrupt FLAG Register – GIFR Bit 7 6 5 4 3 2 1 0 $3A ($5A) INTF1 INTF0 – – – – – – Read/Write R/W R/W R R R R R R Initial value 0 0 0 0 0 0 0 0 GIFR • Bit 7 – INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the corresponding Interrupt Flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 bit in GIMSK, are set (one), the MCU will jump to the Interrupt Vector.
• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on PD6(ICP) (i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero.
AT90S2313 • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag.
• Bit 4 – SM: Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle mode is selected as sleep mode. When SM is set (one), Power-down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes”. • Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK Register is set.
AT90S2313 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File, SRAM and I/O memory are unaltered. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
The four different prescaled selections are: CK/8, CK/64, CK/256, and CK/1024, where CK is the Oscillator clock. For the two Timer/Counters, added selections such as CK, external clock source and stop can be selected as clock sources. 8-bit Timer/Counter0 Figure 29 shows the block diagram for Timer/Counter0. The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external p in .
AT90S2313 Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 ($53) – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. • Bits 2,1,0 – CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0 The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer/Counter0. Table 7.
16-bit Timer/Counter1 Figure 30 shows the block diagram for Timer/Counter1. Figure 30. Timer/Counter1 Block Diagram T1 The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Register (TCCR1B). The different Status Flags (Overflow, Compare Match and Capture Event) and control signals are found in the Timer/Counter Interrupt Flag Register (TIFR).
AT90S2313 Timer/Counter1 can also be used as an 8-, 9-, or 10-bit Pulse Width Modulator. In this mode the counter and the OCR1 Register serve as a glitch-free standalone PWM with centered pulses. Refer to page 35 for a detailed description of this function. The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register (ICR1), triggered by an external event on the Input Capture Pin (ICP).
• Bits 1, 0 – PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode is described on page 35. Table 9.
AT90S2313 • Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 10. Clock 1 Prescale Select CS12 CS11 CS10 Description 0 0 0 Stop, the Timer/Counter1 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T1, falling edge 1 1 1 External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
AT90S2313 The TEMP Register is also used when accessing TCNT1 and OCR1A. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1 (OCR1A) form an 8-, 9-, or 10-bit, free-running, glitch-free and phase-correct PWM with output on the PB3(OC1) pin.
During the time between the write and the latch operations, a read from OCR1A will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A. When the OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the next compare match according to the settings of COM1A1/COM1A0. This is shown in Table 13. Note: If the Compare Register contains the TOP value and the prescaler is not in use (CS12..
AT90S2313 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted. See Table 14 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to 1 before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog. • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
AT90S2313 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Powerup/down.
EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 $1C ($3C) – – – – – EEMWE EEWE EERE Read/Write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EECR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
AT90S2313 Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
UART The AT90S2313 features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART).
AT90S2313 tus Register (USR) is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit Shift Register.
found to be logical “1”s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the Transmitter Shift Register as they are sampled.
AT90S2313 UART Control The UART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 $0C ($2C) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 UDR The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read.
• Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incoming character is zero). The FE bit is cleared when the stop bit of received data is one. • Bit 3 – OR: OverRun This bit is set if an OverRun condition is detected (i.e., when a character already present in the UDR Register is not read before the next character has been shifted into the Receiver Shift Register).
AT90S2313 • Bit 1 – RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. • Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.
UART Baud Rate Register – UBRR Bit 7 6 5 4 3 2 1 0 $09 ($29) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 UBRR The UBRR Register is an 8-bit read/write register that specifies the UART Baud Rate according to the formula on the previous page. Analog Comparator The Analog Comparator compares the input values on the positive input AIN0 (PB0) and the negative input PB1(AIN1).
AT90S2313 • Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector.
I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B Port B is an 8-bit bi-directional I/O port.
AT90S2313 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin.
Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 38.
AT90S2313 Figure 39. Port B Schematic Diagram (Pin PB3) RD MOS PULLUP RESET Q R D DDB3 C WD DATA BUS RESET R Q D PORTB3 C PB3 RL WP RP WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB COM1A0 COM1A1 OUTPUT MODE SELECT COMP. MATCH1 Figure 40.
Figure 41. Port B Schematic Diagram (Pin PB5) Figure 42.
AT90S2313 Figure 43. Port B Schematic Diagram (Pin PB7) Port D Three I/O memory address locations are allocated for the Port D: one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.
Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Bit 7 6 5 4 3 2 1 0 $12 ($32) – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $11 ($31) – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $10 ($30) – PIND
AT90S2313 • INT1 – Port D, Bit 3 INT1, External Interrupt Source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. • INT0 – Port D, Bit 2 INT0, External Interrupt Source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. • TXD – Port D, Bit 1 Transmit Data (Data Output pin for the UART).
Figure 45. Port D Schematic Diagram (Pin PD1) RD MOS PULLUP RESET Q R D DDD1 C DATA BUS WD RESET R Q D PORTD1 PD1 C RL WP RP WP: WD: RL: RP: RD: TXD: TXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN TXD Figure 46.
AT90S2313 Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) RD MOS PULLUP RESET Q R D DDDn WD RESET R Q D PORTDn PDn DATA BUS C C RL WP RP WP: WD: RL: RP: RD: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5 0, 1 SENSE CONTROL CSm2 CSm1 TIMERm CLOCK SOURCE MUX CSm0 Figure 48.
Memory Programming Program and Data Memory Lock Bits The AT90S2313 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21. The Lock bits can only be erased with the Chip Erase operation. Table 21. Lock Bit Protection Modes Memory Lock Bits Mode LB1 LB2 1 1 1 No memory lock features enabled. 2 0 1 Further programming of the Flash and EEPROM is disabled.(1) 3 0 0 Same as mode 2, and verify is also disabled.
AT90S2313 within the self-timed write instruction in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 22. Table 22. Supply Voltage during Programming Part Serial Programming Parallel Programming 2.7 - 6.0V 4.5 - 5.5V AT90S2313 Parallel Programming This section describes how to parallel program and verify Flash Program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S2313.
Table 23. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 DATA PB7 - 0 I/O Function Bi-directional Data Bus (Output when OE is low) Table 24. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS) 0 1 Load Data (High or Low data byte for Flash determined by BS) 1 0 Load Command 1 1 No Action, Idle Table 25.
AT90S2313 5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 26 for tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY pin. Programming the Flash A: Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2.
The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: • The command needs only be loaded once when writing or reading multiple memory locations. • Address high byte needs only be loaded before programming a new 256-word page in the Flash. • Skip writing the data value $FF; that is, the contents of the entire Flash and EEPROM after a Chip Erase.
AT90S2313 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” for details on command and address loading): 1. A: Load Command “0000 0010”. 2. B: Load Address High Byte ($00 - $03). 3. C: Load Address Low Byte ($00 - $FF). 4. Set OE to “0”, and BS to “0”. The Flash word low byte can now be read at DATA. 5. Set BS to “1”. The Flash word high byte can now be read from DATA. 6. Set OE to “1”.
Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 63 for details on command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS to “1”. The status of the Fuse and Lock bits can now be read at DATA (“0” means programmed). Bit 7 = Lock Bit1 Bit 6 = Lock Bit2 Bit 5 = SPIEN Fuse bit Bit 0 = FSTRT Fuse bit 3. Set OE to “1”. Observe that BS needs to be set to “1”.
AT90S2313 Parallel Programming Characteristics Figure 52. Parallel Programming Timing tXLWL tXHXL XTAL1 tDVXH tXLDX tBVWL Data & Contol (DATA, XA0/1, BS) Write tWLWH WR tRHBX tWHRL RDY/BSY tWLRH tXLOL tOHDZ tOLDV Read OE DATA Table 26. Parallel Programming Characteristics, TA = 25°C ± 10%, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.5 IPP Programming Enable Current tDVXH Data and Control Setup before XTAL1 High 67.0 ns tXHXL XTAL1 Pulse Width High 67.
Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 53. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. Figure 53. Serial Programming and Verify 2.7 - 6.
AT90S2313 ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2.
Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $7F. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $7F, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte.
AT90S2313 Serial Programming Characteristics Figure 55. Serial Programming Timing MOSI tOVSH SCK tSHOX tSLSH tSHSL MISO tSLIV Table 29. Serial Programming Characteristics, TA = -40°C to 85°C, V CC = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Min 1/tCLCL Oscillator Frequency (VCC = 2.7 - 6.0V) tCLCL Oscillator Period (VCC = 2.7 - 6.0V) 1/tCLCL Oscillator Frequency (VCC = 4.0 - 6.0V) tCLCL Oscillator Period (VCC = 4.0 - 6.0V) tSHSL Typ 0 Max Units 4.0 MHz 250.0 ns 0 10.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
AT90S2313 Notes: External Clock Drive Waveforms 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3.
Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
AT90S2313 Figure 58. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 12 10 TA = 25˚C TA = 85˚C I cc(mA) 8 6 4 2 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA= 25˚C 8 Vcc= 6V 7 Vcc= 5.5V 6 Vcc= 5V Vcc= 4.5V I cc(mA) 5 Vcc= 4V 4 Vcc= 3.6V Vcc= 3.3V Vcc= 3.0V 3 Vcc= 2.
Figure 60. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 3.5 3 TA = 25˚C I cc(mA) 2.5 TA = 85˚C 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 61. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 2 TA = 85˚C 1.8 1.6 I cc(µΑ) 1.4 1.2 1 TA = 70˚C 0.8 0.6 0.4 0.2 TA = 45˚C 0 TA = 25˚C 2 2.5 3 3.5 4 4.5 5 5.
AT90S2313 Figure 62. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 160 140 TA = 25˚C 120 I cc(µΑ) TA = 85˚C 100 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 63. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 0.9 0.8 0.7 TA = 25˚C 0.6 I cc(mA) TA = 85˚C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.
Note: Analog Comparator offset voltage is measured as absolute offset. Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 65. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. Vcc = 2.
AT90S2313 Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 30 I ACLK (nA) 40 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VIN (V) Figure 67. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25˚C 1400 TA = 85˚C F RC (KHz) 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.
Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 68. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 69. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 15 I OP (µA) 20 10 5 0 0 0.5 1 1.5 2 2.
AT90S2313 Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25˚C 60 TA = 85˚C 50 30 I OL (mA) 40 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 72. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 10 I OL (mA) 15 5 0 0 0.5 1 1.5 2 VOL (V) Figure 73. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 3 I OH (mA) 4 2 1 0 0 0.5 1 1.5 2 2.
AT90S2313 Figure 74. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 Vcc Figure 75. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 Input hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C page 16 $3E ($5E) Reserved SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 17 – – – – – – page 22 $3D ($5D) SPL $3C ($5C) Reserved $3B ($5B) GIMSK INT1 INT0 $3A ($5A) GIFR INTF1 INTF0 $39 ($59) TIMSK TOIE1 OCIE1A – – TICIE1 – TOIE0 – page 23 $38 ($58) TIFR TOV1 OCF1A – – ICF1 – TOV0 – page 24 $37 ($57) Reserved $36 ($56) Reserved –
AT90S2313 Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd − Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd − K Z,C,N,V,H 1 SBIW Rdl, K Subtract Immediate fro
Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, -X Load Indirect and Pre-Dec. X ← X − 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc.
AT90S2313 Ordering Information Speed (MHz) Power Supply Ordering Code Package 4 2.7 - 6.0V AT90S2313-4PC AT90S2313-4SC 20P3 20S Commercial (0°C to 70°C) AT90S2313-4PI AT90S2313-4SI 20P3 20S Industrial (-40°C to 85°C) AT90S2313-10PC AT90S2313-10SC 20P3 20S Commercial (0°C to 70°C) AT90S2313-10PI AT90S2313-10SI 20P3 20S Industrial (-40°C to 85°C) 10 4.0 - 6.0V Operation Range Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.
Packaging Information 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – D 25.984 – E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.
AT90S2313 20S 20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 0.51(0.020) 0.33(0.013) 7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 2.65 (0.1043) 2.35 (0.0926) 0.30(0.0118) 0.10 (0.0040) 0.32 (0.0125) 0.23 (0.0091) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches REV.
AT90S2313 Table of Contents Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 Pin Descriptions.................................................................................................... 3 Crystal Oscillator.............................
Parallel Programming ......................................................................................... Parallel Programming Characteristics ................................................................ Serial Downloading ............................................................................................. Serial Programming Characteristics ................................................................... 61 67 68 71 Electrical Characteristics...........................................
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