Manual

iv
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
19.5 Functional Description ........................................................................121
19.6 Shutdown Controller (SHDWC) User Interface ..................................123
20 Bus Matrix .................................................................................129
20.1 Description .........................................................................................129
20.2 Memory Mapping ................................................................................129
20.3 Special Bus Granting Techniques ......................................................129
20.4 Arbitration ...........................................................................................130
20.5 Bus Matrix User Interface ...................................................................133
20.6 Chip Configuration User Interface ......................................................139
21 External Bus Interface (EBI) ....................................................143
21.1 Description .........................................................................................143
21.2 I/O Lines Description ..........................................................................145
21.3 Application Example ...........................................................................147
21.4 Product Dependencies .......................................................................149
21.5 Functional Description ........................................................................149
21.6 Implementation Examples ..................................................................157
22 Static Memory Controller (SMC) .............................................169
22.1 Description .........................................................................................169
22.2 I/O Lines Description ..........................................................................169
22.3 Multiplexed Signals ............................................................................169
22.4 Application Example ...........................................................................170
22.5 Product Dependencies .......................................................................170
22.6 External Memory Mapping .................................................................171
22.7 Connection to External Devices .........................................................171
22.8 Standard Read and Write Protocols ...................................................175
22.9 Automatic Wait States ........................................................................184
22.10 Data Float Wait States .....................................................................189
22.11 External Wait ....................................................................................193
22.12 Slow Clock Mode ..............................................................................199
22.13 Asynchronous Page Mode ...............................................................202
22.14 Static Memory Controller (SMC) User Interface ...............................205
23 DDR/SDR SDRAM Controller (DDRSDRC) .............................211
23.1 Description .........................................................................................211
23.2 DDRSDRC Module Diagram ..............................................................212
23.3 Product Dependencies .......................................................................213