Manual

v
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.4 Functional Description ........................................................................216
23.5 Software Interface / SDRAM Organization, Address Mapping ...........230
23.6 DDR-SDRAMC User Interface ...........................................................232
24 Burst Cellular RAM Controller (BCRAMC) .............................245
24.1 Description .........................................................................................245
24.2 BCRAMC Block Diagram ....................................................................246
24.3 Product Dependencies .......................................................................247
24.4 Functional Description ........................................................................248
24.5 BCRAMC User Interface ....................................................................257
25 Error Corrected Code (ECC) Controller .................................267
25.1 Description .........................................................................................267
25.2 Block Diagram ....................................................................................267
25.3 Functional Description ........................................................................267
25.4 Error Corrected Code (ECC) Controller User Interface ......................272
26 DMA Controller (DMAC) ..........................................................277
26.1 Description .........................................................................................277
26.2 Block Diagram ....................................................................................278
26.3 Functional Description ........................................................................280
26.4 DMA Controller Software Requirements ............................................307
26.5 DMA Controller (DMAC) User Interface .............................................309
27 Peripheral DMA Controller (PDC) ...........................................335
27.1 Description .........................................................................................335
27.2 Block Diagram ....................................................................................336
27.3 Functional Description ........................................................................337
27.4 Peripheral DMA Controller (PDC) User Interface ...............................340
28 Clock Generator .......................................................................349
28.1 Description .........................................................................................349
28.2 Slow Clock Crystal Oscillator ..............................................................349
28.3 Main Oscillator ....................................................................................349
28.4 Divider and PLL Block ........................................................................351
29 Power Management Controller (PMC) ....................................354
29.1 Description .........................................................................................354
29.2 Master Clock Controller ......................................................................354
29.3 Processor Clock Controller .................................................................355