Manual

124

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

19.6.3 Shutdown Mode Register

Access Type: Read/Write

• WKMODE0: Wake-up Mode 0

• CPTWK0: Counter on Wake-up 0

Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-

up event occurs. Because of the internal synchronization of WKUP0 , the SHDN pin is released

(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.

• RTTWKEN: Real-time Timer Wake-up Enable

0 = The RTT Alarm signal has no effect on the Shutdown Controller.

1 = The RTT Alarm signal forces the de-assertion of the SHDN pin.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––––RTTWKEN

15 14 13 12 11 10 9 8

––––

76543210

CPTWK0 – – WKMODE0

WKMODE[1:0] Wake-up Input Transition Selection

0 0 None. No detection is performed on the wake-up input

0 1 Low to high level

1 0 High to low level

1 1 Both levels change