Manual

149
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and
the CompactFlash slot.
2. Any PIO line.
3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see ”NAND Flash Sup-
port” on page 155.
21.4 Product Dependencies
21.4.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface
pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the
application, they can be used for other purposes by the PIO Controller.
21.5 Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the
external memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
• the Static Memory Controller (SMC)
• the DDR/SDRAM Controller (DDR/SDRAMC)
• the Burst Cellular RAM Controller (BCRAMC)
• the ECC Controller (ECC)
• a chip select assignment feature that assigns an AHB address space to the external
devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable CompactFlash support logic
• programmable NAND Flash support logic
SDCK CLKCLK––––
SDCKN –CLKN––––
SDCKE/BCCRE CKE CKE CRE – – –
DQS0 - DQS1 –DQS0 - DQS1––––
RAS/BCADV RAS RAS ADV – – –
CAS/BCOE CAS CAS OE – – –
SDWE/BCWEWEWEWE–––
BCOWAIT – – OWAIT – – –
NWAIT – – – WAIT WAIT –
Pxx
(2)
– – – CD1 or CD2 CD1 or CD2 –
Pxx
(2)
–––––CE
Pxx
(2)
–––––RDY
Table 21-3. EBI Pins and External Devices Connections (Continued)
Signals
Pins of the Interfaced Device
SDRAM Mobile DDR
Burst
CellularRAM
CompactFlash
CompactFlash
True IDE Mode
NAND Flash
Controller DDR/SDRAMC DDR/SDRAMC BCRAMC SMC