Manual

188
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
22.9.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See Figure 22-16 on page 185.