Manual

19
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Note: 1. DDR Port 2 or Port 3 is selectable for each master through the Matrix Remap Control Register.
Table 7-3. AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access
Master 0 1 2 3 4 5 6 7 8 9 10 11
Slave
ARM926 Instruction
ARM926 Data
Peripheral DMA Ctrl
LCDCtrl
USB High Speed
Device Ctrl
Image Sensor Interface
DMA Ctrl
Ethernet MAC
OHCI USB Host Ctrl
MP Block Master 0 MP Block Master 1 MP Block Master 2
0
Internal SRAM
32 Kbytes
XXXX X XXXXXXX
1
MP Block
Slave 0
XXXX X XXXXXXX
2
Internal ROM X X X X X X X X X X X X
LCD
Controller
User Interface
XX-- - ----XXX
USB High
Speed Device
Interface
XX - - - - X - - X X X
OHCI USB
Host Interface
XX-- - ----XXX
3
MPBlock
Slave 1
XXXX X XXXXXXX
4
External Bus
Interface
XXXX X XXXXXXX
-
- DDR Port 0 X - - - - - - - - - - -
5 DDR Port 1 - X - - - - - - - - - -
6 DDR Port 2 X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
DDR Port 3 X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
X
(1)
7
MPBlock
Slave 2
XXXX X XXXXXXX
8
MPBlock
Slave 3
XXXX X XXXXXXX
9
Internal
Peripherals
XX X - - - X - - X X X