Manual

20
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
7.6 Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-two Channels
– Two for each USART
– Two for the Debug Unit
– One for the TWI
– One for the ADC Controller
– Two for the AC97 Controller
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the each Multimedia Card Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
– DBGU Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– AC97 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC1 Transmit Channel
– SSC0 Transmit Channel
– DBGU Receive Channel
– TWI Transmit/Receive Channel
– ADC Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– AC97 Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC1 Receive Channel
– SSC0 Receive Channel
– MCI1 Transmit/Receive Channel
– MCI0 Transmit/Receive Channel
7.7 DMA Controller
• Acting as one Matrix Master