Manual

225
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 23-12. Self Refresh Mode Entry, Timeout =0
Figure 23-13. Self Refresh Mode Entry, Timeout =1 or 2
Figure 23-14. Self Refresh Mode Exit
NOP READ BST NOP PRCHG NOP ARFSH NOP
0
Trp
Enter Self refresh
Mode
SDCK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[0:1]
Da Db
D[15:0]
3
DM[1:0]
NOP READ BST NOP
0
Da Db
64 or 128
wait states
3
PRCHG NOP ARFSH NOP
Trp
Enter Self refresh
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
D[15:0]
DM[1:0]
NOP VALID NOP
0
TXNRD/TXSRD (DDR device)
TXSR (Mobile DDR device)
TXSR (Mobile SDR, SDR-SDRAM device)
Exit Self Refresh mode
clock must be stable
before exiting self refresh mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
DaDb
D[15:0]
3
DM[1:0]