Manual

233

6264A–CAP–21-May-07

AT91CAP9S500A/AT91CAP9S250A

23.6.1 DDRSDRC Mode Register

Access Type: Read/Write

Reset Value: See Table 23-8

• MODE: DDRSDRAMC Command Mode

This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini-

tialize the SDRAM device and to activate deep power-down mode (see Figure on page 231).

31 30 29 28 27 26 25 24

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23 22 21 20 19 18 17 16

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15 14 13 12 11 10 9 8

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76543210

––––– MODE

MODE Description

000 Normal Mode. Any access to the DDRSDRAMC will be decoded normally

001 The DDRSDRC issues a NOP Command when the SDRAM device is accessed regardless of the cycle.

010 The DDRSDRC issues an All Banks Precharge Command when the SDRAM device is accessed regardless of the cycle.

011

The DDRSDRC issues a Load mode Register command when the SDRAM device is accessed regardless of the cycle.

The address offset with respect to the SDRAM device base address is used to program the mode register. For instance,

when this mode is activated, an access to the DDRSDRAMC_base + offset address generates a load mode register

command with the value offset written to the SDRAM device mode register.

100

The DDRSDRC issues an Auto Refresh Command when the SDRAM device is accessed regardless of the cycle.

Previously, an All Banks Precharge Command must be issued.

101

The DDRSDRC issues an Extended Load Mode register command when the SDRAM device is accessed regardless of

the cycle. The address offset with respect to the SDRAM device base address is used to program the mode register. For

instance, when this mode is activated, an access to the DDRSDRAMC_base + offset address generates a extended load

mode register command with the value offset written to the SDRAM device extended mode register.

110 Deep power mode: Access to deep power-down mode

111 Reserved